Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
the best way to know ant clock gating and how it can be implemented for a RTL level design please refer Design compiler manual .. there are soem very good papers clock gating ... .
in short wat we can say abt clock gating is:
In order to reduce the dynamic r switching power dessipation a group of FFs in a design can be gated with an appropraite gating ckt .. this means if a FF with a MUX which feeds back the data wen there is no new data ..the mux will be replaced with a CG ckt .. which is transperent wen ever there is data change on data lines and will disconnect the clock other wise thus saving dynamic powr..
let me know if u want any more ...
u told clock gating at RTL level....coming to physical level for a pshyical design engg....what he/she can do for clock gating....i guess u got my point hw important is clock gating in respect to a Physical design engg........
The clock gating will offcouse effect the skew. since at any time if there is new data available the Gating ckt wil have to pass the data to the input of the FF and there is delay beacuse of CGckt . and hence this could lead to clock skew ...
Well yes .. since clockgating using DC where CG can be initialiased i think the tool can place soem buffers for the faster clock so as to counter the clockgated paths .. i am though not very much clear of this ...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
