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iir implementation in fpga problem!!!!!!!!!

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rsrinivas

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Hi all,
I have a problem.
I am into designing an array of bandpass filters so that it forms a filter bank.
I have designed the filter in matlab using fdatool and generated the hdl (verilog)
code from it.it's a 6'th order bpf with 3 biquads(IIR Butterworth).
pls do let me know that if i can reuse this filter.i.e i am using a serial
architecture to process the samples and the coefficients are stored in a rom.
how do i effectively reuse the delay sections.

any suggestions or help would be greatly appreciated.

cheers
srinivas
 

of course, you can implementation IIR as a FIR filter, and only with one multiplier.

such as y(n) = b(0)*x(n) + b(1)*x(n-1) + a(0)*y(n-1). You can use register store x(n), x(n-1) and y(n-1), and Time division using the multiplier, and accumulute three multiplier outputs to get y(n). After get y(n), replace y(n-1) register with y(n), and same to x(n) and x(n-1), and then you can get y(n+1) as y(n).

Maybe misunderstanding your requirement.
 

Hi
Thanks for the reply.
I can do it but as i have quantized the filter scaling has been introduced.
What i want to have is a filter bank so i think i can reuse the filter coefficients by putting them in a ROM. But how do i handle the delay sections.As i am planning to have a serial architecture the context of each filter stage(a stage is one among the number of filters in a filter bank)has to be preserved.Can i do it.

Thanks in advance

cheers
Srinivas
 

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