Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

BIASING OF SOURCE AND DRAIN JUNCTIONS IN MOS ?

Status
Not open for further replies.

its_thepip

Member level 2
Joined
Sep 15, 2006
Messages
43
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
1,513
why reverse biased juction nmos

Hi
In MOS , there are two pn junctions formed
1) Between n+ Source and PSubstrate
2)Between n+ Drain and PSubstrate
In Kang,I read that these junctions are always reverse biased ...
How does this happen ??
If the junction 1 is to be reverse biased , then source has to be at a higher potential than the Psubstrate
But to eliminate the body effect , we short the substrate and source....
In this situation , how does the source-substrate be reversie biased ???
 

mos substrate biasing

In MOS , there are two pn junctions formed
1) Between n+ Source and PSubstrate
2)Between n+ Drain and PSubstrate
In Kang,I read that these junctions are always reverse biased ...
How does this happen ??

This is the reason that normally bulk of PMOS always connected to supply while bulk of NMS always connected to lowest supply (VSS).

If the junction 1 is to be reverse biased , then source has to be at a higher potential than the Psubstrate
But to eliminate the body effect , we short the substrate and source....
In this situation , how does the source-substrate be reversie biased ???

Normally we only short substrate and source for differential pair, as we want to avoid Vth fluctuation due to change of Vsb and avoid supply noise directly coupled to differential pair via substrate. In this case, source-substrate will neither be reversed biased nor forward biased.
 

forward biasing substrate source drain nmos

we short the substrate and source....
In this situation , how does the source-substrate be reversie biased ???

This is valid for three terminal MOS.

If you want reverse bias you need four terminal MOS.
 

source biasing mos

in real fact. all mos are 4 terminal devices. generally, there are 2 operating.
(use nmos for example)
1. source and bulk(substrate or pwell) connect together. based on standard cmos process, there are not isolated P-well, so, bulk is directly connected to substrate together with source, without body effect.

2. bulk connects to lowest votlage(lower than source, otherwise, bulk source pn junction will forward bias). this can be seen in source follower, switch application et al.

In all cases, PN junction will not forward bias, but will zero bias or reverse bias
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top