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What is strange Verilog??

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abdalla

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please i`m asking about this code


.......
always@(CLK)
begin

out<=in1*in2;

end
.........

or.

.......
always@(CLK)
begin

out<=in1<<in2;

end
.........


when i synsthiess those code no problem and no error how...as i know thoses functions need many clk cycles to be done for example left shifting for 4 digit need at least 4 clk ..but in the simulation(modelsim) the result is shifted 4 digit in one cycle only
 

What you have written according to it both the multiplication and
shifting should complete in one clock cycle only. For modelsim you are
not providing any timing information. So it generates no error.

To do shifiting of data in single clock one needs what is known as barrel
shifter circuit! and not shift register.
 

thx..but i`m really new in that world ..why when i said out<=in1/in2;
i got error in synsthesis but no problem in model sim
 

Thats because divider is far more complex in hardware than
multiplication operation. Most of the time FPGA has 18 by 18 multipliers
inbuild. But no divider logic!
 

really thx....last question (today:D)

It may be trivial but i need it ...how to initalize output in verilog 95

module koko(me);

output [10:0]me;
:
:


HOW to initilze me??
by Zero
 

after little search i found that i can initial any register in Verilog 2001(not in verilog 95)..but when i synthesize i got erro..ok you say those initialize for simulation only ok...but i need to make register initalized with a certain value..how can i do it
 

abdalla said:
after little search i found that i can initial any register in Verilog 2001(not in verilog 95)..but when i synthesize i got erro..ok you say those initialize for simulation only ok...but i need to make register initalized with a certain value..how can i do it
Click to expand...

Hi,
use reset signal, on reset initialize your register with the desired value.

thanks
sawaak
 

you can initialize your register in FPGA with constrains.
 

Hi dude,

Even if you code the design as in1<<in2, it will be converted into a combinational logic by the synthesis tool. Hence the computation will be finished in one clock cycle.

Division in velog will throw a synthesis-error, "divisor should be an integral multple of 2".
We have to use other way for modeling this.
I was working with only powers of 2, and hence wrote case statements. Please let me know if there is abetter way of doing it.

Regards
"enjoy your work"
 

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