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setup and hold time theoritically

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sandysuhy

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Hi All,
Is there any topic to calculate setup and hold time theoritically.How can you estimate setup and hold time theoritically.

Thanks in advance.
sandy
 

setup and hold time are documented in the library.

chek this one "Calculating the setup and hold times at the pins of a chip":
**broken link removed**
 

Hi ray123,
From my understanding it is for whole chip, but i need for flip-flops.
 

Tclock_to_q + Tcombinational_logic + Tdff_setup - Tskew< Tclock_cycle.
Tclock_to_q + Tcombinational_logic + Tskew > Thold
 

sandysuhy said:
Hi All,
Is there any topic to calculate setup and hold time theoritically.How can you estimate setup and hold time theoritically.

Thanks in advance.
sandy
Click to expand...

Please refer to the similar topics pasted on this web or you can check the book titled Digital Design Perspective which i remember describe the structure of DFF as well the cause of existence for setup and holdtime.

Good luck,

Thomson
 

Tc2q + Tc + Ts - Tsk< Tclk.
Tc2q + Tc + Tsk > Th

Tc2q = Clock to Q delay
Tc = Combinational logic delay
Ts = Setup time
Tsk = Clock skew
Tclk = Clock period
Th = Hold time

These equations also helps in determining the fastest clk speed at which the design can work.

Best Regards,
Harish
https://hdlplanet.tripod.com
https://groups.yahoo.com/group/hdlplanet
 

you can refer artisan's ASIC lib to find dff's schematic,

then you can estimate DFF's setup and hold time from delay and logic.


best regards



sandysuhy said:
Hi All,
Is there any topic to calculate setup and hold time theoritically.How can you estimate setup and hold time theoritically.

Thanks in advance.
sandy
Click to expand...
 

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