How to convert testcase writen in ntb into spice stimulus?

vcd2vec

Dear all

I have a digital design writen in verilog .

after synthesis, i want to simulate in the transistor level using nanosim .

and i've translate the verilog netlist into spice netlist using nettran command in hercules .

and I want to also translate the testcase written in ntb in to spice stimulus or anyother vector file that

nanosim can recognize .

In general , my OVF( Original Vector File ) is testcace in ntb

my TVF( Target Vecyor File ) is spice stimulus or other format that nanosim can recognize

I have looked up to VTRAN , but it seems that it can't deal with my problem , it can translate

verilog-testbench in to ns-sported vector file.

thx in advance

,what should I do then ?

Added after 4 hours 17 minutes:


hello all :

I looked up in the nanosim userguide , and found the vcd2vec command .

i'll try this command .

and i know vcd files contain both the test vector and response .

i wonder if i get the vec file ,whether it also contain these all , and can verify if the design have the right

response in transister-level through nanosim .

Added after 1 hours 45 minutes:


I found the vcd2vec command , vcd2vec <-d > -nvcd vcd_file <-nsig sig_file> <-nvec vec_file>

but i can't find any more information about this command either in the ns-userguide or command-reference .

because i'm a newbie , i don't know what is the signal information file .

how can i get the file , or how can i write such a file .

i use vcs simulator , and generate the vcd file , can i generate this signal information file also by vcs , how ?

thx all .