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Internal Error in Quartus...HELP

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btminzon

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Hi, i,m tring to compile my project, but when i use the operator "&" to concatenate two bytes in a word, and use it, this error apears:

"*** Fatal Error: Module: quartus_map.exe Exception: Access Violation
Stack Trace:
End-trace
"

I think that the qu(at)rtus stack pointers overflown....somebody help me? thanks!!!!
 

Hi btminzon:
I found the same problem using special characters of my own language. For instance "à" or "é" and so on (naming files in Nios II project).
Then it is better do not use it these special characters.

Pont de Pedra
 

Internal Error in qu(at)rtus...HELP

btminzon.. using the concatenate operator will not cause the prob...

normally the internal error is cause by the hdl code u write.. there is some weird behavior of the code... try write it in another way...

or u can report the bug to altera on their website.. they are happy to know tht...

currently, quartus II v6.0 sp1 is the latest release..

regards,
sp
 

Hey SP, thanks for the tip. I tried to shift 8 times to left, and use, istead of concatenate, but the same error apear...I'll report to Altera, and i'm already using Quartus 6.0 SP1....The same problem apeard in Quartus 6.0...But, anyway, i'll continue trying...

Regards
 

Internal Error in qu(at)rtus...HELP

welcome... but i think u still are doing the same thing..

just understand tht the concatenation is not the problem...

the flow of ur hdl is the cause of the internal error... mayb u can post ur code here... i might not able to fix it.. but other might b able to check for u...

i hav the same prob as u since the max+plus II generation... normally, i change the flow of my hdl and it is ok then...

regards,
sp
 

Hi SP, here is my code, in JPEG format. I tried everything, since concatenating until extended the 8 bit vector to 16, and after making a boolean OR with two vector....all results in the same internal error. Tnks
 

Internal Error in qu(at)rtus...HELP

i think u are kinda software guy... am i right?...

i am not expert first thing... but the way u write is kinda like normal programming... u must imagine wad hardware u are coding...

first... the divide_clk process seems weird.. i hope u are trying to make a slower clk for ur design.. but seems like it is not...

emm another thing is tht VHDL has the if-elsif statement... and u are not using it...

it would b better if u could tell us wad your hdl code trying to do... and please post the code... we wont sell ur code :p

sorry if i offense u...

regards,
sp
 

Hi SP.... Tnks for the advice. Yes, i'm a computer engineering, and i started to use vhdl.
This code is to generate a pwm, but very fast. The input clock is about 8Mhz, and i need to reduce it to 1Mhz. Each 1Mhz clock must count in high the number defines in "Data" (TON) and after, start automatcaly counting the number in Low, defined by also by "Data" (TOFF). I need 8 bits, because i had to link this fpga with a PLC that uses a 80C32 with 8 bit bus, but, 8 bits its too bad, i need at least 11. So that's why i need to concatenate... were I clear? if not, i explain better (i can try :) ). Thansk again!!!

Regards
 

Please post code with "code tags" as in the following code. Use the Quote button in the thread box to see how it's done.

This is bad style for synthesis, as it forces the synthesis tool to create a number of latches. Instead of selecting where the data goes, it is better to select where the data comes from.

Because you have no clock'event condition, the entire process is asynchronous. This is especially bad for the following assignment:

ton_toff <= not ton_toff;

That creates unchecked feedback from output to input. If you were to succeed in generating a configuration file, you would have a hot spot on your chip.

Creating a 32-bit number is rather meaningless when your target integer has a range of 0 to 900.

"dados" is not used in this process - I assume you mean "data".

Code:
choose: process(EAB01,dados,start)
begin
if (Start = '0') then
    if (EAB01 = "01") then
        buffer_ton_16 <= data;
    else if (EAB01 = "10") then
        buffer_toff_16 <= data;
    else if (EAB01 = "11") then
        if (ton_toff = '0') then
            buffer_ton_32 <= data;
        else if (ton_toff = '1') then
            buffer_toff_32 <= data;
        end if;
        end if;
        ton_toff <= not ton_toff;
    else if (EAB01 = "00") then
        TON  <= CONV_INTEGER(buffer_ton_16 & buffer_ton_32);
        TOFF <= CONV_INTEGER(buffer_toff_16 & buffer_toff_32);
    end if;
    end if;
    end if;
    end if;
    end if;
end process;
 

Internal Error in qu(at)rtus...HELP

sorry for the delay... busy on work

normally i used this algorithm to do my clk divider in my FPGA development board.

Code:
library ieee; 
use ieee.std_logic_1164.all; 
  
entity clk_div is 
port 
(clk_crystal, reset: in std_logic; 
 clk_desired: buffer std_logic); 
end clk_div; 
  
architecture arc_clk_div of clk_div is 
begin

-- P = f(crystal)/(2*f(desired))
-- this is the formula for counting the constant P
-- f(crystal) is the external crystal frequency
-- f(desired) is the slower clk frequency required by the designer

	process(reset, clk_crystal) 
		variable count: natural;
		constant P : natural := 33330;
	begin 
		if reset = '1' then 
			count := 0; 
			clk_desired <= '0'; 
		elsif rising_edge(clk_crystal) then 
			count := count + 1; 
			if count = P then 
				clk_desired <= not clk_desired; 
				count := 0; 
			end if; 
		end if; 
	end process; 
end arc_clk_div;

please note tht the usage of signal and variable in a process in VHDL matter a lot...

regards,
sp

Added after 6 minutes:

normally if u wanna do counter like in C... use variable instead of signal, as variable assignment is instanteneous, but not signal... it is quite hard for me to explain, i would refer u to the <Circuit Design With VHDL, V. A. Pedroni; MIT Press> for further and detail explanation...

regards,
sp
 

yes, the difference between usage of signal and variable i know. The signal just will assigne after the process, while variable assigne instantanealy, but the usage os variable makes a lot of macrocell consumption. But tnks for this algorith, i liked very much. i'd like to talk more with you. find me in msn (btminzon at hotmail) or email (btminzon at yahoo com br).

best regards


Breno
 

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