Cadence: No schematic, only netlist, how to simulat?

I've a netlist that describe a circuit.

In cadence, generally, we draw schematic and a corresponding symbol. We then connect the symbol with Signal source for simulation.

Instead of schematic, can I draw a symbol that point to this netlist and then connect the symbol with signal source for simulation? Can it be done and how?

yes, general, i think you can make a symbol for simulation.
just modify the cdf information of the symbol (please pay more attention you need select BASE and the io name should be same), add the netlist as a model file of the symbol, and then include the netlist in analog artist windows, then you regenerate the testbench's netlist from artist and see if the netlist is included ,if yes, you can do the simulation as you know, that's all.

a simple way is just build a blank schematic with your test bench (your signal), then include the cirsuit netlist in the include path, use ADE create netlist to see if your netlist is right then simulate it

I think I know what you mean. I am also having the same problem here. I got the model file from the manufacturer but I just cant get simulator to work. Can anyone guide me with the step?:idea: ??



This is the model file I was refering to. I have also attached a zip file fo the model file.

*FF123P at Temp. Electrical Model
*-------------------------------------
.SUBCKT FF123P 20 10 30 50
*20=DRAIN 10=GATE 30=SOURCE 50=VTEMP
Rg 10 11x 1
Rdu 12x 1 1u
M1 2 1 4x 4x DMOS L=1u W=1u
.MODEL DMOS PMOS(VTO=-1 KP=8.6
+THETA=.166667 VMAX=9.5E5 LEVEL=3)
Cgs 1 5x 620p
Rd 20 4 4.5E-3
Dds 4 5x DDS
.MODEL DDS D(M=2.14E-1 VJ=7.6E-2 CJO=290p)
Dbody 20 5x DBODY
.MODEL DBODY D(IS=1.4E-9 N=1.389551 RS=.00095 TT=20.8n)
Ra 4 2 4.5E-3
Rs 5x 5 0.5m
Ls 5 30 0.5n
M2 1 8 6 6 INTER
E2 8 6 4 1 2
.MODEL INTER PMOS(VTO=0 KP=10 LEVEL=1)
Cgdmax 7 4 580p
Rcgd 7 4 10meg
Dgd 4 6 DGD
Rdgd 4 6 10meg
.MODEL DGD D(M=1.6E-1 VJ=1.09E-4 CJO=580p)
M3 7 9 1 1 INTER
E3 9 1 4 1 -2
*ZX SECTION
EOUT 4x 6x poly(2) (1x,0) (3x,0) 0 0 0 0 1
FCOPY 0 3x VSENSE 1
RIN 1x 0 1G
VSENSE 6x 5x 0
RREF 3x 0 10m
*TEMP SECTION
ED 101 0 VALUE {V(50,100)}
VAMB 100 0 25
EKP 1x 0 101 0 .025
*VTO TEMP SECTION
EVTO 102 0 101 0 .0008
EVT 11x 12x 102 0 1
*DIODE THEMO BREAKDOWN SECTION
EBL VB1 VB2 101 0 .08
VBLK VB2 0 20
D DB1 20 DBLK
.MODEL DBLK D(IS=1E-14 CJO=.1p RS=.1)
EDB 0 DB1 VB1 0 1
.ENDS FF123P

cufriend said:

*FF123P at Temp. Electrical Model
*-------------------------------------
.SUBCKT FF123P 20 10 30 50
*20=DRAIN 10=GATE 30=SOURCE 50=VTEMP
Rg 10 11x 1
Rdu 12x 1 1u
..........
.ENDS FF123P

Click to expand...

It's a subcircuit netlist not a simple transistor model, so u should use it as a subcircuit in your simulation.

hi peterelec,

How do I go about doing that? Can you guide me along? Thanks for your help