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queue depth in FIFO for memory controller

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rakesh_aadhimoolam

rakesh_aadhimoolam

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heelo folks,i am doing a project memory controler design,i am not able to find out the queue depth of FIFO at the processor side.i need ya help from ya all people

thanks in advance
 

i think you need to be more specifiv about your project.

what is the memory controller for (sram,sdram,ddr,ddr2)
what is the processor.
what are the clock rates.
what are the busses.
what kind of transfers you want to use. (singel, bursts, pages)
 

kindly specify your read cycle and write cycle time
 

rakesh_aadhimoolam said:
heelo folks,i am doing a project memory controler design,i am not able to find out the queue depth of FIFO at the processor side.i need ya help from ya all people

thanks in advance
Click to expand...


sorry for not informing about the specifications.Actually,Iam fixing the specifications.Instead the assumptions are:
1)The processor clock rate is twice the data transfer rate into the memory.
2)Data width is 1byte.Data is sent in bytes every processor clock pulse.
3)Memory is designed in banks each having fixed size.Each memory location is 8-bit width.
I want to know at what frequency my controller has to be fixed.Its true that it depends on the queue depth.but how?
Please let me of any other info u want.
Thanks
 

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