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Need of Hold time in Max frequency calculation?..

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varatharajan

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maximum clock frequency calculation

Hi all..
Whether we have taken into account the hold time while calculating the maximum frequency of digital circuits?..

regards,
Varatharajan
 

setup hold max frequency

No, hold time is not required , Set up time is required.
 

why hold time max frequency

Hold violation have no relationship with clock period, because the timing check will be occured at the same clock edge.
however for the setup timing check, check will be occured in one clock cycle.
 

max frequency calculation

Hi,

It has become necessary to perform hold analysis in worst case corner. I can think of 3 reasons:

1. Useful skew. If there is a large skew in the clock tree (e.g. to meet setup time), it is possible that this can cause a hold violation in worst corner, but not best corner

2. Negative setup and negative hold in worst case cell timing

3. OCV (on-chip variation). In best case hold analysis, and worst-case setup analysis, we usually only scale the clock path. In worst-case setup analysis, we have to scale the data path, thus less margin for hold in worst case.

Regards,
Eng Han
www.eda-utilities.com
 

what is hold time analysis

See the link below abt the discussion for the same topic.
 

Let us take an example, if setup time Ts = 2 ns , clock to Q(FF prop delay) Tpff = 0 ns and Combinatinal dealy Tp = 0 ns, Hold time Th = 2 ns .

For the above case what is the maximum clock frequency? whether hold time needs to be accounted or not?

And If we change(increase) the clock frequency,whether the hold time will be violated or not?..
 

For the given example if we calculate the max frequency of operation
by the formula fmax = tseup+tclk->q + tcombo
it will give 2ns and if we operate with 2ns clock the hold time will fail and circuit will not work properly.

So we have to have 2ns delay in datapath which in turn will cause a clock period of 4ns and reduce the maximum
frequency of operation.
 

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