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Error Amp phase margin VS. stability analysis of LDO....

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neter

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ldo phase margin

Deal all,

My error amp design spec is follow:

DC gain : >90dB
UGB : 8MHz
Phase margin : >70 degree.
C_load=70pF

but I connect PMOS pass element(Close-Loop) and re-simulaion,The error amp
phase margin changed from 70 degree to 26 degree.

How can i do design sufficient phase margin (close-loop > 60 degree)?

Thanks a lot
 

ldo stability analysis

Dear neter,

A phase margin of about 40 degrees is more than enough with the settling in a LDO with a switching load. It is mighty difficult to use a PMOS drop out transistor or a very low drop out and get a very high stability in a 60 degree phase margin. Also, ESR of the load capacitance can also determine the phase margin.

When you test the stability, you should do the loop gain test and not the open loop test in order to ascertain the phase margin.

I hope this note helps
 

amp phase margin

neter said:
but I connect PMOS pass element(Close-Loop) and re-simulaion,The error amp
phase margin changed from 70 degree to 26 degree.

How can i do design sufficient phase margin (close-loop > 60 degree)?

it's quite normal. as you can see at opamp's response, dominant pole is about 100Hz.
when you add pmos pass device you already have 2 low frequency poles which worsen phase margin. surely you do esr compensation, but maybe this is not enough.
do you really need so high gain? i would exchange it for lower output resistance.
unless low power loss is your main goal
 

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