neter
Member level 2
ldo phase margin
Deal all,
My error amp design spec is follow:
DC gain : >90dB
UGB : 8MHz
Phase margin : >70 degree.
C_load=70pF
but I connect PMOS pass element(Close-Loop) and re-simulaion,The error amp
phase margin changed from 70 degree to 26 degree.
How can i do design sufficient phase margin (close-loop > 60 degree)?
Thanks a lot
Deal all,
My error amp design spec is follow:
DC gain : >90dB
UGB : 8MHz
Phase margin : >70 degree.
C_load=70pF
but I connect PMOS pass element(Close-Loop) and re-simulaion,The error amp
phase margin changed from 70 degree to 26 degree.
How can i do design sufficient phase margin (close-loop > 60 degree)?
Thanks a lot