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Mismatch in minimum clock period between primetime and vsim

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maverick_mind

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Putting the timing constraint as 1.8 ns I did synthesis and PnR. the Design Compiler, Encounter successfully did SPnR. There are no violation in Primetime reports.

But when I run my post synthesis design in modelsim at this clock period, I get $ recovery errors. I can only run my design at 2.4 ns clock period correctly.

Can anyone explain me the mismatch between synthesis constraint timing and post synth simulation timing.
 

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