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Design rules and guidelines for 6T SRAM cell based on TSMC035

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Antonio_Magma

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Hi guys, i am to design a 6T SRAM cell based on TSMC035.

Where can i find 'design rules' or guidelines for TSMC035? Such as the distance (lambda) between metal and poly etc.

I'm still very new to this, so i need help. Thanks guys.
 

Re: 6T SRAM

It depends if you are using staggered or stretched topology.

Usually, a rule of thumb for the spatial gap between metal-metal, metal-poly and poly-poly should be at least 2λ (gate length) apart in a 6T SRAM cell.

Try to use poly as far as possible in the cell for better conductivity, minimises the possibility of electromigration and flicker noise. Use metal1 when you connect Word Line, Bit Line, VDD and VSS.

Check out Berkeley Lecture Notes.
 

Re: 6T SRAM

Given any technology, say 0.35um, there are different flavors (if you can say) on fab sequence thereby "creating" multiple "design rules".

If you are a student in an Univ, then the department should "help" you in getting the design rules. Better yet, ask your prof. He/She should know where the things are.

Srivatsan

P.S.: I checked MOSIS.ORG, here is one link which can help you.
**broken link removed**
 

6T SRAM

Thx for the design rules.

How about transistor sizing? I do not know how to go about it. Where should i start?

I've read Rabaey's book and it seems for 6T SRAM, the whole idea about sizing is such that to prevent the potential at Q to flip the other inverter for both READ and WRITE cases.

Added after 10 minutes:

I've currently drawn the schematic of the 6T SRAM using SWCAD III. However, for LVS i need to use TANNER.

Which netlist file (.net / .cir) should i used for TANNER? Because i can't seem to find a compatible one.
 

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