Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

simple question about NMOS when Vg=0

Status
Not open for further replies.

Chethan

Full Member level 3
Joined
Jul 11, 2005
Messages
171
Helped
20
Reputation
40
Reaction score
12
Trophy points
1,298
Location
Bangalore
Activity points
2,837
Hi all,

Please see the following circuit from the book Sedra and Smith. Here the transistor is in saturation even when the gate voltage Vg = grounded. I want to know , when the gate has been grounded there is no positive charges on the gate. Hence no inversion takes place below the gate and no channel is formed. If there is no channel at all then how is that there is a current flow and the transistor is in saturation. Please excuse me if the question is very simple.

thanx in advance
chethan
 

It's not JUST the gate voltage, what matters is the gate-source voltage (gate voltage - source voltage).

In the picture, the gate voltage is grounded. You have TWO supplies in the picture, a positive 2.5V and a negative 2.5V.

==> Let us say that the source voltage in the picture is -1.0V (I'm just making up numbers here to go along with my example). The gate voltage is 0V. So your gate-source voltage is (0V) - (-1V) = 1V. If 1V is greater than the threshold voltage, you could indeed get current to flow in the transistor.
 

    Chethan

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top