Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
You can refer to layout example in
[1] Jan Rabaey, "Digital Integrated Circuits 2nd Edition"
[2] Neil Weste, "CMOS VLSI Design A Circuits and Systems Perspective (3rd Edition)"
[3] Neil Weste, "Principles of CMOS VLSI Design"
[4] Baker, "CMOS Circuit Design, Layout, and Simulation"
You can use tools like LASI, Microwind, Cadence, or other EDA-CAD layout tools. Even Protel can be used.
In practice, the lambda λ scale is used. For example, if I use a 0.18um CMOS technology, then the channel length is 0.18um.
Therefore we use two λ equals to 0.18um.
In practice, to design a CMOS inverter, follow the steps below:
1. Draw the diffusion layers of the PMOS and NMOS. Make sure they have the same diffusion length (not the channel length), but the diffusion width of the PMOS must be 2.5 times longer than the diffusion width of the NMOS. This is to compensate the low mobility of holes by decreasing the cross-sectional channel resistance, in order to match the mobility of electrons.
For example, both diffusion length have 10 λ each, the diffusion width of NMOS be 6 λ, then the diffusion width of PMOS be 15 λ in this case.
2. You can choose to place an N-well to encompass PMOS or a P-well to encompass NMOS. Normally this depends on the choice of your substrate (usually an epitaxy layer). If you use a N-type substrate, then you use a P-well for NMOS. If you use a P-type substrate, then you use an N-well for PMOS. You need to use a metal layer, metal1, to connect either
(1) VDD to the N-well or (2) VSS to P-well.
Make sure you use multiple vias for this connection so that you can reduce the body effect to the minimum. If you are using an N-well for PMOS, then you have to make a contact potential using a via and metal1 that connects this well to VDD. Likewise use a via and metal1 that connects the substrate to VSS for the NMOS.
Always connect this contact potential closest and around your transistor (defined by the diffusion layer). This is to reduce body effect.
3. Draw poly-Si (polysilicon) which is 2 λ (mask channel length, not effective channel length) across
(1) the middle of the diffusion layer of PMOS.
(2) the middle of the diffusion layer of NMOS.
Notice the poly-Si you drew for PMOS is longer than the NMOS because the diffusion layer of PMOS is longer.
Make sure you make a 2 λ poly-Si tail or extension out of the diffusion for both NMOS and PMOS. This tail is in the opposite direction of where you will later connect the two poly-Si.
The drain and source are on either side of diffusion layer equally divided by the poly-Si.
4. Connect the two poly-Si you drew for PMOS and NMOS. In the centre of this connection, make a metal1 connection using a via to your input, Vin.
5. Use metal1 and vias to connect the drain of PMOS and NMOS. This is is extended out for your output, Vout.
6. Connect the VDD to the Source of PMOS. Connect the VSS to the Source of NMOS. Make sure you use multiple vias for these connections. This is to reduce resistance, thus minimizes latchup.
7. Usually transistors are aligned in a very organised fashion.
In digital circuits using a P-substrate or epitaxy layer, a long N-well is used where many PMOS can be placed in this long well.
Therefore the VDD rail and VSS rail are parallel to both side of the well. This is to allow ease of drawing the transistors.
To imagine this, try imagine a picture where you are hanging many clothes on a long metal bar in your wardrode.
The book "CMOS Digital Integrated Circuits: Analysis and Design" by Sung-Mo Kang and Yusuf Leblebigi has a few version of inverter layouts and they are in colour.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
