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An ideal clock has rising and falling edges each separated in time by exactly Ts seconds (Ts is the time period). Due to some non-idealities, the edges occur at nTs ± Tj seconds (n is an integer). This deviation Tj is called jitter. The sigma-delta ADC has a clock which drives the comparator. Due to jitter, the ideal time instants when the comparator samples its input signal changes and this causes degradation in SNR. This SNR degradation is more severe for a continuous time sigma-delta ADC (as opposed to discrete time where jitter is less severe) as it affects the width of the feedback DAC current pulse. You can think of jitter error as error in the amount of charge that is fed back to the loop filter (current pulse integrated over time ,(area) gives charge). This addition of jitter noise is similar to any signal non-idealities and is not shaped by the noise transfer function. Jitter is not a significant problem in discrete time ADC.
Dither is a known out of band frequency signal that is injected by the designer in a sigma-delta ADC (usually at the comparator input). Dither actually helps in spreading the inherent quantization noise over frequency (and improves SNR). It also helps to make the ADC more stable. As far as i know, dither is added specifically to improve the ADC's performance - hence its advantages outweigh the disadvantages , otherwise it will not be used!. A good article on dither in sigma-delta ADC can be found here (both are the same, one is html and other is pdf format) :
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