Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Creating LEF to pass on to the backend tools

Status
Not open for further replies.

r_p_sanna

Member level 3
Joined
Oct 18, 2004
Messages
65
Helped
6
Reputation
12
Reaction score
5
Trophy points
1,288
Activity points
569
Regd: Creating lef

Hi,
If i have a RTL design containing memories, is there any way i can create the lef to pass on to the backend tools?
 

Regd: Creating lef

does anyone have lef/def userguide ?
 

Re: Regd: Creating lef

Go to Silicon Integration Initiative (Si2), http://www.si2.org/
-------------------------------------------------------------------------
LEF DEF Format Specification
**broken link removed**
 

Re: Regd: Creating lef

hi,
what you want is a whole flow.
you have to p&r your design and generate gds, and then suing abstract from c@dence to extract lef file.
or you can use encounter or astro to extract lef,but accuracy is a matter.
 

Regd: Creating lef

hi linuxluo,
yes, i agree with you about creating lef. this is almost like backtracking. What i was thinking was, along with the netlist, if it has memories, then, a lef will be given so that the memory can be made into a blackbox in the netlist during the semi-custom flow. my question is:

do you take the memory's netlist alone through the complete flow and generate the lef file?

in this way, can we generate the physical information of the memory and create a blackbox that can be used along with other netlists ??

Hope i'm clear. Incase if i'm not please let me know.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top