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signed addition in verilog

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superhet

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verilog addition

im doing a project in which i need to add two signed numbers. how can i check for underflow and overflow?

Code: 
module stimulus;

reg signed [7:0] a,b;
wire signed [7:0] c;

signed_adder my_adder(a,b,c);

initial
begin
$monitor($time, " a = %d,  b = %d, c = %d", a, b, c);
end

initial
begin
	a = 127; b = 127;
end

endmodule

module signed_adder(a,b,c);

input signed [7:0] a,b;
output signed [7:0] c;

assign c = a+b;

endmodule

the above simulation gives me 127+127=-2

can somebody help??????????
 

verilog signed addition

the width a, b, and c are all 8 bits
8 bits can present -128~127 only
but 127+127=254, but c is only 8 bits
so the results is wrong
so the width must be 9 bits at least
the code is as follow
wire [8:0] c;
assign c={a[7],a}+{b[7],b};
 

verilog signed

Hi tarkyss

Code: 
assign c={a[7],a}+{b[7],b};
We must do like this ?
I feel following description is ok
Code: 
module signed_adder(a,b,c); 

input signed [7:0] a,b; 
output signed [8:0] c; 

assign c = a+b; 

endmodule
 

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