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Need help in regards to low jitter PFD topologies

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Lightening

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Hi All

Anybody have experience with Low jitter PFD topologies. Not at the gate but basic building block level.

So, I am confussed over various text that desscribe Alexander, Hogge and the the basic PFD using two D flip flops and a nand gate with feeding back to the reset via delay circuit.

Which circuit has best phase noise performance, no dead zone and most importantly why.

My application is at quiet low frequency < 100MHz. Of course in general the faster the circuit the less jitter.

All help very much appreciated.

Thanks Lightening
 

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