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The trick is to bias the gates of the cascode devices at the right level.
In the diagram, delta V refers to the vdsat of M3, M4, M5, M6.
See image 1 below.
If we bias the gate of M6 at Vgate_6 = Vdd - Vt - 2 delta V. then the
max output voltage that will still keep our transistors in saturation is
vout_max = Vgate_6 + Vt = Vdd - 2 delta V.
This is for a pmos.
For nmos, it is the same idea. You just have to bias the gate of M7, and M8 at Vt + 2Vdsat_8.
Then Vout_min = Vgate_8 - Vt = 2 Vdsat.
See diagram4 below.
The entire lecture slides is here:
**broken link removed**
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