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- 8th November 2005, 10:43 #1
## static cmos

Hello everyone,

How to compare static CMOS with dynamic logic from speed and power's view?

- 8th November 2005, 10:43

- 9th November 2005, 15:44 #2

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## static cmos dynamic cmos

what does dynamic logic means?

- 9th November 2005, 16:05 #3
## dynamic cmos logic

Originally Posted by**anjali**

Just like Dynamic CMOS logic,C2MOS, etc.

- 9th November 2005, 16:05

- 11th November 2005, 17:29 #4

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## static vs dynamic logic power

dynamic CMOS logic - more or less like pseudo nmos/ generic logic. only dynamic power dissipation like pdyn= CL*Vdd^2.

well static CMOS and Dynamic CMOS logics have their advantages and disadvantages.. if you go in for dynamic logic.. cascading is not possible as in evaluation stage the transition from 0-1 doesnt occur as PDN would be disabled. like u need to add an invertor to the dynamic cascaded CMOS to obtain domino logic.. this is how is it..static CMOS is also ok.. it has its own disadvantages..but static COS logic requires more transistors for implementing the logic.. somethin like N+2.. but in dynamic logic this is an attempt to reduce the number of transistors required to implement the logic.. somethin like N+1.

correct me if i am wrong..

with regards,

arun

- 13th November 2005, 16:15 #5
## power consumption in static and dynamic logics

The Complementary CMOS circuit design falls under two categories:

*1. Static*

2. Dynamic

**1.Static CMOS**

In*Static*CMOS design, at every point in time, each gate output is connected to either Vdd or Vss via a*low-resistance*path. Also, the outputs of the gate assume at all times the value of the Boolean function implemented by the circuit.

A Static CMOS gate is a combination of two networks - the*pull-up netowrk (PUN)*and the*pull-down network (PDN)*. The function of the PDN is to provide a connection between the output and Vdd anytime the output of the logic gate is supposed to be**1**. Similarly, the PDN connects the output to Vss anytime the output is supposed to be**0**.

The PUN and PDN networks are constructed in a mutually exclusive manner such that one and only one of the networks is conducting in steady state.

The Static CMOS gates have*rail-to-rail*swing ,**no static power dissipation**. The speed of the static CMOS circuit depends on the transistor sizing and the various parasitics that are involved with it. The problem with this type of implementation is that for*N*fan-in gate*2N*number of transistors are required, ie, more area required to implement logic. This has an impact on the capacitance and thus the speed of the gate.

**2. Dynamic CMOS**

Dynamic CMOS circuits rely on the temporary storage of signal values on the capacitance of high-impedance circuit nodes. These circuits also have no static power dissipation and uses a sequence of*precharge*and conditional*evaluation*phases with the addition of a clock input.

The main advantages of the Dynamic CMOS logic are increased speed and reduced implementation area. Fewer devices are used to implement a given logic, this reduces the overall load capacitance and thus increases the speed.

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- 13th November 2005, 16:15

- 15th November 2005, 04:32 #6

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## sizing of static cmos gates

i think in modern digital technology, full-static CMOS is dominated,especially considering power consumption.

dynamic CMOS is great in speed before 0.35um era,but now , static one is fast enough , because of large number of transistors in die ,power consumption became bottleneck, so dynamic CMOS is not popular anymore.

- 18th November 2005, 06:27 #7

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## cmos domino logic

For dynamic logic you also need to consider leakage, noise and clk skew related problems which become really hard problems in current deep submicron technology.

Circuits robustness is alway more important than speed, especially in technologies below 90nm.

- 6th August 2007, 02:33 #8
## dynamic logic advantages and disadvantages

About Static vs Dynamic area. It is not always true that Dynamic is smaller. It depends on the logic fuction and implementation. For example, the Dynamic Inverter, 1 PMOS and 2 NMOS is larger than the Static Inverter, 1 PMOS and 1 NMOS.

Also, it is correct that the Static implementation is more popular.

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