Thomson
Full Member level 3
ahb monitor
hi,
Although i've used PCI monitor before (written by Phoenix), and i've searched the web for long time, i'm still rather confused about how to write a qualified AHB Monitor to be embedded in the current SoC system based on AHB bus.
First i've little experience of using OVL(OpenVErilog library) and of using systemVerilog to perform the assertions writing, it's really hard for me to do the job from the scratch. Currently i've listed all the possible features that the AHB bus will encounter within the application, which include the AHB Master/Slave and so on, but to what extent shall these features be realized using Verilog or SystemVerilog to better match the SoC's application?
I really need your advice on implementing such monitor if you have conducted it before!
Thanks in Advance!
Thomson
hi,
Although i've used PCI monitor before (written by Phoenix), and i've searched the web for long time, i'm still rather confused about how to write a qualified AHB Monitor to be embedded in the current SoC system based on AHB bus.
First i've little experience of using OVL(OpenVErilog library) and of using systemVerilog to perform the assertions writing, it's really hard for me to do the job from the scratch. Currently i've listed all the possible features that the AHB bus will encounter within the application, which include the AHB Master/Slave and so on, but to what extent shall these features be realized using Verilog or SystemVerilog to better match the SoC's application?
I really need your advice on implementing such monitor if you have conducted it before!
Thanks in Advance!
Thomson