how to confirm the L of MOS in analog circuir?

hell all:

I have a question: in analog circuit, I find most MOS transistor's Length is so larger than MOS in digital circuit. I do nott know why.

In fact, I think the length should be short, because short L an short wideth can produce small capacitance.

thanks.

Lambda------ channel length modulation coefficient.
The longer the channels L, the smaller the Lambda.

If you use small length, the short channel effect is very critical. You must make sure the application of this MOSFET(for dc bias or amplifier). In some condition, smaller length has better efficiency. It is really depended on your application.

also matching sould be considered in analog circuit design, if you use the minimum length permited by the process, the matching will be bad.

I know the channel length modulation coefficient. But if matching sould be considered, why the length of MOSFETs in analog circuit is difference?

ΔL is little dependent on L.
If two MOSs have 0.35u of drawing L, the real L may be 0.36u and 0.34u. For 2u of drawing L, the real L may be 2.01u and 1.99u. The latter is better for matching.

yes
on the other hand, consider the layout place and route.

Besides what mentioned above, long L contributes to decreasing MOS flicker noise (1/f) , but also slowing the circuit speed.

I rember a sentence in the book writed by Allen: the longer L can cause larger gain. and why?

wjxcom said:

I rember a sentence in the book writed by Allen: the longer L can cause larger gain. and why?

Click to expand...

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Increasing L of the output transistors will increase the Ro , hence increase gain. If you increase the L of the tail transistor, it will help to increase the CMRR. The penalty is higher parasitic capacitor.


regards,
smart

Hi,

The sizing of L is depend on type of application when u design a circuit. Mostly in the high frequency signal path, the size of L is to keep the min as in the design manual, in order to avoid parasitics cap which will degrade bandwidth. Like in the the design of differential amplifier, the L size of the tail transistor will be kept 2 or 3 times higher than the min L size in order to minimize the channel length modulation, lambda effect. Thus u will have constant current altough the tail voltage change.


"I rember a sentence in the book writed by Allen: the longer L can cause larger gain. and why?"

Regarding this question, the output impedance of a transistor is given as ro = 1/LAMBDA (Id). And also u know that L = 1/ Lambda. Meaning that in order to reduce the lambda effect, the L need to be large. Then when L is large, it will increace the output impedance on the transistor, according to the formula and also this will indirectly increase the gain as A = gmro.

Hope this helps you.
Regards,
suria3

But in Professor baker discusses in his latest book .Keep the length short for DSM designs.Anybody can through some light on this statement


rgds
Prabhu

reduce leff effect?

Well I think in Analog design it's hard to indicate spacific answer.

In digital, we need a low capacitance in order to reduce the switching time thus resulting faster I/O relationship.

In Analog, we use the function of transistor for amplifying. The Gain is given by (CMOS for ex) = (W/L)n/(W/L)p...( this also according to the schematic design)
This ex for diff amp.

Well, genrally the ratio give tha gain. And in analog the input is from poly, and that signal is transfered and processed to be output. Unlike digital, the voltage is given by the VDD, poly signal is only to trigger the transistor on/off (act like a switch).

So we need a good area of transistor, big in order to get better current flow and electron migration.

Big length increasing the resistance but according to CMOS dynamic power =
P= CVdd²f or if you turn f=1/t and t=RC

Big resistance giivng low power dissipation.

Hi all:

I do not know how to confirm the L of MOS in annlog circuit. For this circuit, I find the length of the circuit is different. If we want to void channel length modulation and we want to consider matching, I think all the MOS can have have the same length, such as 2um. But in this circuit, the lenght is not same.

I do not know why?

To understand the circuit you posted, best is to understand the basic principles of analog design mentioned by others posted earlier here or by me posted below.


What is the critical issue in CMOS analog design? Flicker noise and mismatches.

Someone mentioned Flicker or 1/f noise that predominates any other noises at low frequencies. That's very good!
Mean Vn² = (1/f).K/Cox.W.L, thus larger L and/or W to decrease 1/f noise. This is one of the many reasons why some low-speed or low-frequency designs still prefer to use 0.25 or 0.35 or even 0.5 since there is no need to invest so much money for 0.13 if only low-noise performance is needed, and not high-speed.

However 1/f noise is not a serious issue at high-frequency analog circuits. It is critical for Low IF receiver and low-frequency/low-speed designs, however.

Despite this 1/f noise, it is peak at DC, thus high-frequency circuits aren't not spared. Therefore in high-frequency circuits, DC/static/quiescent power dissipation must be reduced to the minimum, especially in the biasing.

Gm is directly proportional to W/L. Larger L decreases Gm, thus reduces CMRR, PSRR. This is not very wise. The choice is either to decrease L or increase W.

Smaller L also primarily aims to push maximum bandwidth, increases output impedance, density and compatibility with digital. Relatively, decreasing L allows W to be decreased too, by same proportion or ratio, thus increases maximum bandwidth. Decreasing L is also used when W becomes so large as in a wide transistor that the use of a interdigitated transistor is unavoidable.

Analog designers have to compromise W/L either increasing W or decreasing L.

There is however one drawback of increasing W - increased parasitics Cgd and Cgs that increase Miller Effect, thus limiting maximum bandwidth.

Theoretically smaller L looks good but in practice, it is not easier to achieve due to matching problems.

You normally see performance analog circuits still done at higher L at 0.25 or even 0.5. The reason being that it is harder to match, due to process variation, in smaller L. Matching is better at higher L.

With the above reasons mentioned, analog is usually not done below 0.18-µm, despite attempts in 0.13-µm and even 90nm however with very bad matching.

Another reason is the model used. Analog designs these days are done with short-channel devices, despite the scaled-reduction in Vdd to reduce short-channel effects. If you still think that you are using long-channel devices, your design will never work. Models offered to you by foundry is a very deterministic factor. It affects your HSPICE simulation and confidence to succeed.

Right now, TSMC and UMC offers the best models for analog because of very low process variations. If you use IBM, STMicro, Chartered, NEC, or even AMI, your designs are likely to fail.

In digital where a minimum-sized transistor can achieve ratioless CMOS logic without using larger transistors unless for driving or large fan-out purpose. This favours reduction in area, parasitics, delay and loading, for high density, speed and lower power dissipation.

In analog, the art is different. We play with W/L for Gm, CMRR, PSRR, SNR, Ft, ro, noise reduction, slew rate, biasing and power consumption, feedback & stability, and many more tradeoffs.

Unlike digital, there is no noise margin to tolerate noises and offsets in analog. Every little variation causes error that must be compensated or tuned for, else it gets amplified or accumulated to the output.