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Yes you can. But if u use a very high frequency the std cells will be upsized unecessarly and will result in higher area/power for the design .. Typically for prelayout synthesis a 10% overconstrained clock is used.
Yes, you can do it. It makes the job for P&R tool easier when you are doing a timing driven routing. But remember, if you set the clock frequency much higher than real clock, it may cause inefficient results in respect to power and area. So just define an acceptable margin for that clock and do synthesis based on it.
ooops, It seems when I was typing the reply, Wizkid replied faster. Thanks to wizkid.
Yes.
If you set the clock frequency much higher , it may cause inefficient results in respect to power and area.
So you can set a small value higher than the actual clock.
about 10% higher.
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