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Depends on your STA constraints, and how much you cover in GLS.
But in general, GLS may uncover problems with cross clock domain boundaries, reset sequence and X-propatation.
STA is only as good as the effort put into the contstraints. For a complex design, with multiple clock domains, gate level sims are always useful for finding those false paths that you thought were false, but really aren't.
Gate-level simulation can help to identify those timing exceptions, such as
1) false_path(s)
ex. cross clock domains
2) multi-cycle path(s)
ex. re-timing by synthesis tool
Due to these timing exceptions maybe not correctly described in the timing constraints for STA.
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