# Wish to know more about Johnson Counter...

1. ## Wish to know more about Johnson Counter...

Attached schematic diagram is a Johnson Counter. Would you pls advise while "Loop 2" is considered to be INVALID?

Also, pls suggest few applications for Johnson Counter.

Thanks.

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2. ## Wish to know more about Johnson Counter...

hey obtain some information here
Code:
```hxxp://www.play-hookey.com/digital/johnson_counter.html
hxxp://en.wikipedia.org/wiki/Counter

and also there is some datasheet w/ application at
http://www.dieelektronikerseite.de/D...Philips%29.pdf```

3. ## Wish to know more about Johnson Counter...

Well its not invalid in the sense that the particular sequence is not possible.
These counters are used for timing sequence generation.
So the outputs of two Flip-Flops are Anded in a particular way such that you get a timing sequence with frequency of one eight(in this case) that of the clock pulse.
In johnson counters once they get into one particular sequence they can't get out of it and get stuck in a infinite loop. So if that particular sequence is such that the reqd timing sequence is not generated from it its called invalid.

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4. ## Re: Wish to know more about Johnson Counter...

Originally Posted by usernam
Well its not invalid in the sense that the particular sequence is not possible.
These counters are used for timing sequence generation.
So the outputs of two Flip-Flops are Anded in a particular way such that you get a timing sequence with frequency of one eight(in this case) that of the clock pulse.
In johnson counters once they get into one particular sequence they can't get out of it and get stuck in a infinite loop. So if that particular sequence is such that the reqd timing sequence is not generated from it its called invalid.
Thanks usernam. Would you pls advise which two of flip-flops that you meant in "... the outputs of two Flip-Flops are Anded..."? I could not see how the outputs "Anded"... pls advise.

For the particular circuit shown in my first post, can I say that the 'reqd timing sequence' is 1/8 of the clock pulse frequency?

"So if that particular sequence is such that the reqd timing sequence is not generated from it its called invalid."
I still don't really get your point here. Is it possible to explain, based on the example given in the figure, why Loop 2 is considered invalid? Did you mean the whole string (Q3 Q2 Q1 Q0) or pattern should be repeated 1/8 of clock frequency, or each output (e.g. Q2)? Thanks.

5. ## Re: Wish to know more about Johnson Counter...

Well if you want just one timing sequence then you can go with any one of a number combinations. For example take Q0'.Q3' or say Q0.Q1'.This will give you a timing sequence with one eight clock frequency. Say you wanted two timing seqs which are shifted from each other by a time 2T where T is the clock time period then you could use Q0'.Q3' and Q0.Q2'.
Now suppose you have setup and AND gate to give an output Q0'.Q3' for a timing sequence based on Loop 1. Now suppose your johnson counter wslippe dinto loop 2 somehow then you don't get your reqd timing sequence.

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6. ## Wish to know more about Johnson Counter...

For normal operation, all the outputs will either be set to '1', or reset to '0'. Can you pls advise in which situation that a Johnson counter will be slipped into invalid loop?

7. ## Re: Wish to know more about Johnson Counter...

Some basics of the Johnson Counter:
It is a "non-constant-weighted" counter. This means that there is no numeric value that is assigned to any of the bit positions.
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The sequence is one of many sequences that comprise the family of "cyclic counters". Cyclic counters have the property that when going from one state to the next one and ONLY one bit changes state. You will notice that the "invalid" loop does not have this property. Most practical implementations of the Johnson counter have an additional decoder to detect an illegal state, and force the counter into a legal state.
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The Johnson counter has some interesting and useful properties:
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. Any state can be decoded with a single 2 input "And" gate
. (assuming the the output and its complement is available
. for each stage)
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. Any consequtive sequence of states can be decoded with a
. single 2 input "And" gate (with the above assumption).
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. The output of the "And" gate decoder will be "glitch-free", since
. one and only one input changes state for any state transition
. of the counter.
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The maximum number of states for a Johnson counter is 2N, vs 2^N for a binary counter.
Regards,
Kral

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