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 24th July 2005, 16:28 #1
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vhdl clock divider
hai friends
i am a beginner in ASIC. In VHDL i was able to design divide by 3 or divide by 5 circuits using FSM.is it possible to get an 2/3 divider circuit ??. actually the problem is to get 33.33 MHZ from an 50 MHZ source.
kindly suggest me some technique to achieve it.
take care
bye
 24th July 2005, 16:28
 25th July 2005, 04:44 #2
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clock divider vhdl
Use PLL to double the clock frequency. Then divide it by 3.
 25th July 2005, 04:46 #3
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clk divider vhdl
Hi,
Use PLL or DCM's to multiply the clock freq by 2. Then divide by three. But just check out, as i think there is some min i/p limit for the i/p frequency to the DCM's.
Best Regards,
 25th July 2005, 04:46
 25th July 2005, 09:05 #4
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clock divider code verilog
Here is one solution!
Hope this helps! Here the divided clock won't have 50% duty cycle!
SORRY the code here is in Verilog. Hope you can convert it to VHDL
easily.
Code:module div_2by3(/*AUTOARG*/ // Outputs clk_2by3, // Inputs clk, reset_n ); input clk, reset_n; output clk_2by3; reg [1:0] clk_by3_pos, clk_by3_neg ; assign clk_2by3 = (~clk_by3_neg[0] & clk_by3_pos[0])  (clk_by3_neg[1] & clk_by3_pos[1]); always @(posedge clk or negedge reset_n) if (!reset_n) clk_by3_pos <= 0; else if (clk_by3_pos == 2) clk_by3_pos <= 0; else clk_by3_pos <= clk_by3_pos + 1; always @(negedge clk or negedge reset_n) if (!reset_n) clk_by3_neg <= 0; else if (clk_by3_neg == 2) clk_by3_neg <= 0; else clk_by3_neg <= clk_by3_neg + 1; endmodule // div_2by3
 25th July 2005, 11:59 #5
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verilog clock double
If u r using FPGA's use DCM's easy and best way
 25th July 2005, 13:43 #6
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clock divider code vhdl
Originally Posted by eeeraghu
i agree , It's best way
 26th July 2005, 09:31 #7
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clk divider 2 vhdl
here goes the VHDL translation for the same code I posted in Verilog
Code:library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clk_div_2by3 is port ( clk : in std_logic; rst_n : in std_logic; clk_2by3 : out std_logic); end clk_div_2by3; architecture clk_div_2by3_arch of clk_div_2by3 is signal clk_div_by3_pos : std_logic_vector(1 downto 0); signal clk_div_by3_neg : std_logic_vector(1 downto 0); begin  behavior clk_2by3 <= (not clk_div_by3_neg(0) and clk_div_by3_pos(0)) or (clk_div_by3_neg(1) and clk_div_by3_pos(1)); pos_edge: process (clk, rst_n) begin  process posedge if rst_n = '0' then  asynchronous reset (active low) clk_div_by3_pos <= (others => '0'); elsif clk'event and clk = '1' then  rising clock edge if clk_div_by3_pos = "10" then clk_div_by3_pos <= (others => '0'); else clk_div_by3_pos <= clk_div_by3_pos + 1; end if; end if; end process pos_edge; neg_edge: process (clk, rst_n) begin  process posedge if rst_n = '0' then  asynchronous reset (active low) clk_div_by3_neg <= (others => '0'); elsif clk'event and clk = '0' then  rising clock edge if clk_div_by3_neg = "10" then clk_div_by3_neg <= (others => '0'); else clk_div_by3_neg <= clk_div_by3_neg + 1; end if; end if; end process neg_edge; end clk_div_2by3_arch;
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