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help on generating a clock

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kyjackchan

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hi there, i am very new to verilog. I am simply writing a clock generator code

The behavioural simulation seems to be ok with clk_output signal giving a clock, but all i could see from the oscilloscope is a high signal for pin 'clk_output', is there anything i'm missing here?

Code: 
module test(clk_output);
	 output reg clk_output;

	initial
		clk_output = 0;

	always
      #10000000 clk_output = ~clk_output;

endmodule
 

u cannot generate a clock inside an FPGA.
ur piece of code cannot be synthesised.
did u check ur synthesis rpt.
it wud have given u a warning telling u abt the removal of those unsynthesised signals.
there won't b any problems with the Behavioral simulation.
 

this is a common misunderstanding in beginners that if you make a clock in simulation you wont need to have a real world clock in your circuit.

in simulation its okay, the clock will be generated. but in a real world implementation you have to have an external clock source connected to some pin of your device.

i hope that helps
 

your code can't be synthesized.

only a simulation model.

best regards



kyjackchan said:
hi there, i am very new to verilog. I am simply writing a clock generator code

The behavioural simulation seems to be ok with clk_output signal giving a clock, but all i could see from the oscilloscope is a high signal for pin 'clk_output', is there anything i'm missing here?

Code: 
module test(clk_output);
	 output reg clk_output;

	initial
		clk_output = 0;

	always
      #10000000 clk_output = ~clk_output;

endmodule
Click to expand...
 

there are many methods to output clock. you can try the method of division of system clock. maybe it can match your need.
 

freeinthewind said:
there are many methods to output clock. you can try the method of division of system clock. maybe it can match your need.
Click to expand...

but even in that case you need a clock "source" from which to divide the clock. so no matter what, you need an external oscillator (its better to use a programmable osc if you need to do experimentation) to drive the logic inside your device.
 

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