Glitches at the output of ideal dac

traceflag verilog

Hi guys,

I am simulating 10bit 50MHz pipelined ADC using HSPICE. To observe the analog output of this ADC, I simply connect the digital bits output to an 10-bits ideal dac. When I observed the output, I get a sinewave representing input voltage with some latency. Also there are glitches at the output of an ideal dac. (I have attached the output file in jpg format).

My questions are:

1) What causes the glitches? Is it because of ideal dac?
2) Is the glitch is an error? Can we neglect it?

cheers

I think that the difference between the clock of ADC and 10bit ideal DAC caused the glitches. The time of ADC's sampling and conventer affect clock. The clock of ADC and DAC are dissimilarity. The glitches wae not affect accurancy of ADC.The time of the glitches was very short ((1/10)*sample period).

do ur ideal DAC contain CLK & DFFs ? if u do have CLK, then u should adjust it to sample the correct output of ADC .

Chenliy, Btrend,

Thanks for your comment. For my ideal dac, i don't use clock. Here is my netlist. Hope you can give comment!

.SUBCKT bitDAC vdd vref+ vref- vout b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b3L
R1 vdd 100meg
R2 0 100meg
X9 b9 b9L BitLogic
X8 b8 b8L BitLogic
X7 b7 b7L BitLogic
X6 b6 b6L BitLogic
X5 b5 b5L BitLogic
X4 b4 b4L BitLogic
X3 b3 b3L BitLogic
X2 b2 b2L BitLogic
X1 b1 b1L BitLogic
X0 b0 b0L BitLogic
ETOTAL vout 0 VOL= '((V(vref+)-V(vref-))/1024)*( (V(b9L)*512) + (V(b8L)*256)+ (V(b7L)*128) + (V(b6L)*64) + (V(b5L)*32) +(V(b4L)*16) + (V(b3L)*8) + (V(b2L)*4) + (V(b1L)*2) + (V(b0L)) ) + (V(vref-)) '
.ends

.SUBCKT BitLogic BX BXL
Vone one 0 DC 1V
gs1 BXL one VCR PWL(1) BX 0 0v,1meg 3.3v,1
gs1c BXL 0 VCR PWL(1) BX 0 0v,1 3.3v,1meg
.ends


Is it something wrong with my netlist that causes the glitch.

many thanks

if u don't use clock to strobe ur output from ADC, u can't guarantee the synchronous of digital input to ur ideal DAC, so ur DAC get glitch.
this is my code for the ideal DAC with clk,

**** Ideal 10bit-DAC generation
.subckt DAC10B DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 AOUT CLK
XLA0 DI0 D0 CLK SH
XLA1 DI1 D1 CLK SH
XLA2 DI2 D2 CLK SH
XLA3 DI3 D3 CLK SH
XLA4 DI4 D4 CLK SH
XLA5 DI5 D5 CLK SH
XLA6 DI6 D6 CLK SH
XLA7 DI7 D7 CLK SH
XLA8 DI8 D8 CLK SH
XLA9 DI9 D9 CLK SH

EDAC2 AOUT 0 VOLT ='LSB*(v(d9)*512+v(d8)*256+v(d7)*128+v(d6)*64+v(d5)*32+v(d4)*16+v(d3)*8+v(d2)*4+v(d1)*2+v(d0))'
.ends

***** switch******
.subckt SW1 in out c cb
*********** define switch turn on voltage at von_th
.param von_th=1
Gsw1 out in VCR PWL(1) c cb 0,100meg 1e-6,1m
.ends

***** S/H ******
.subckt SH in out clk
*********** Sample mode: when clk > vtrig v(out)=v(in) *********
*********** E1 is used for isolating SW1 & SW2 *********
E1 out1 0 VOLT = 'v(outs)'
Xsw1 in outs clk vtrig sw1
C1 outs 0 0.1p $**** added cap will delay the signal & simulated the real case
*********** Hold mode: when clk < vtrig v(out)=v(in) *********
*********** E2 is used for isolating SW2 & OUT *********
Xsw2 out1 out2 vtrig clk sw1
C2 out2 0 0.1p
E2 out 0 VOLT = 'v(out2)'
.ends

is that because of the nonidealization of the clock for adc and dac?
regard

there are also delays in DFF, and other gates after ADC's output. In ideal situation(0s rise/fall time, equal delay time) , if all digital inputs of DAC are sync. there should be no glitch.

The Btrend's saying is right.The fellow is my ideal 10bit DAC with Verilog-A language.

`include "discipline.h"
`include "constants.h"
`define NUM_DAC_BITS 10

module d2a_ideal_1 (clk, din, vout);

input [`NUM_DAC_BITS-1:0] din;
voltage [`NUM_DAC_BITS-1:0] din;

input clk;
voltage clk;
output vout;
voltage vout;
parameter real vmax = 5;
parameter real vmin = 0;
parameter real vth = 1.25;
parameter real trise = 4.0p from (0:inf);
parameter real tfall = 4.0p from (0:inf);
parameter real tconv = 2.0p from [0:inf);
parameter real slack = 10.0p from (0:inf);
parameter integer traceflag = 0;

real lsb, voffset, new_vout;
integer decimal_value;

analog begin

@(initial_step or initial_step("dc","ac","tran","xf")) begin
if (vmin < 0.0 ) voffset = vmin; else voffset = 0.0;
decimal_value = 0;
lsb = (vmax - vmin) / (1 << `NUM_DAC_BITS) ;
if (traceflag) begin
$display("%M DAC range ( %g v ) / %d bits = lsb %g volts.\n",
vmax - vmin, `NUM_DAC_BITS, lsb );
$display(" offset %g volts.\n", voffset );
end
end
@(cross ( V(clk)-vth, 1, slack, clk.potential.abstol)) begin
decimal_value=0;
generate i (`NUM_DAC_BITS-1, 0) begin
decimal_value = decimal_value + (( V(din) > vth ) ? 1 << i : 0 );
end
new_vout = decimal_value * lsb + voffset;

if(traceflag)
$strobe("%M at %g sec. digital in: %d vout: %g",
$realtime, decimal_value, (decimal_value * lsb) + voffset );
end
V(vout) <+ transition ( new_vout, tconv, trise, tfall );
end
endmodule

`undef NUM_DAC_BITS

Million thanks for the wonderful help Btrend and Chenliy.

cheers
-snoop835-

Added after 2 hours 23 minutes:

Hi Btrend,

I have tried your method using idealdac with clock. here is my netlist.

****************************************************************
.OPTION POST
.temp 25
.tran 1ns 1us

xDAC10B DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 AOUT CLK DAC10B

Vb9 DI9 0 pulse (0 5 0 200p 200p 511.8n 1024n)
Vb8 DI8 0 pulse (0 5 0 200p 200p 255.8n 512n)
Vb7 DI7 0 pulse (0 5 0 200p 200p 127.8n 256n)
Vb6 DI6 0 pulse (0 5 0 200p 200p 63.8n 128n)
Vb5 DI5 0 pulse (0 5 0 200p 200p 31.8n 64n)
Vb4 DI4 0 pulse (0 5 0 200p 200p 15.8n 32n)
Vb3 DI3 0 pulse (0 5 0 200p 200p 7.8n 16n)
Vb2 DI2 0 pulse (0 5 0 200p 200p 3.8n 8n)
Vb1 DI1 0 pulse (0 5 0 200p 200p 1.8n 4n)
Vb0 DI0 0 pulse (0 5 0 200p 200p 0.8n 2n)
Vclk CLK 0 pulse (0 5 0 200p 200p 5ns 10ns)

.subckt DAC10B DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 AOUT CLK
XLA0 DI0 D0 CLK SH
XLA1 DI1 D1 CLK SH
XLA2 DI2 D2 CLK SH
XLA3 DI3 D3 CLK SH
XLA4 DI4 D4 CLK SH
XLA5 DI5 D5 CLK SH
XLA6 DI6 D6 CLK SH
XLA7 DI7 D7 CLK SH
XLA8 DI8 D8 CLK SH
XLA9 DI9 D9 CLK SH
EDAC2 AOUT 0 VOLT = 'LSB*(v(d9)*512+v(d8)*256+v(d7)*128+v(d6)*64+v(d5)*32+v(d4)*16+v(d3)*8+v(d2)*4+v(d1)*2+v(d0))'
.param LSB=977uV
.ends

.subckt SW1 in out c cb
.param von_th=1
Gsw1 out in VCR PWL(1) c cb 0,100MEG 1e-6,1m
.ends

.subckt SH in out clk
E1 out1 0 VOLT = 'v(outs)'
Xsw1 in outs clk vtrig sw1
C1 outs 0 0.1p
Xsw2 out1 out2 vtrig clk sw1
C2 out2 0 0.1p
E2 out 0 VOLT = 'v(out2)'
.ends

.probe V(AOUT) V(DI9) V(DI8) V(DI7) V(DI6) V(DI5) V(DI4) V(DI3) V(DI2) V(DI1) V(DI0)
.end
*************************************************************
TEST CONDITION: Input = Ramped-up bits from 0 - fullscale
Fclk = 100MHz
LSB = 1V(fullscale)/1024 = 977uV

I have attached the simulation results in this forum. For some reason I could't get the expected output voltage. The output voltage ramp-up from 0V - 250mV(instead of 1V) and the output curve doesn't look like ideal dac output. I doubt my result is correct. Is is something wrong with my setup? Suggestions?

thanks in advance

sorry, I missed two lines: (which defined the swithing threshold)

VSB VTRIG 0 2.5
.GLOBAL VTRIG

try it again.