assertoin based verification

when is assertion based verification used and where functional verifications lacks its functionality

Writing assertions concurrently with the RTL design and keeping these assertions closely tied to the RTL code are benefitial for both the design and verification processes for digital hardware.

A. The primary benefit is that assertions help to detect more functional bugs, detect them earlier in the process and detect them closer to their original cause. This leads in turn to fewer bugs remaining undetected into production, shorter verification timescales and faster debugging.

B. A secondary benefit is that the very act of formulating and writing assertions can give the designer a better understanding of the design, and hence uncover bugs in the specification or else avoid introducing bugs into the design in the first place.

C. Assertions bring the possibility of increased metrication to the verification process. Assertions directly increase observability of the state of the design during verification. By measuring and controlling the density of assertions and logging assertion passes as well as failures, it is possible to bring some science to the task of knowing when functional verification is complete.

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