[moved] Design and implementation of sigma delta DAC

Dear all,
The requirement is that I have to get an accurate voltage of Vref/4 from the inputs Vref and 0. Hence I am trying to implement a sigma delta DAC for this purpose. Please guide me on how to go about this? Also let me know if there are any other options that I can implement to get the required output.

TIA

Re: Design and implementation of sigma delta DAC

Hi,

do you have to generate/provide an accurate voltage of Vref/4 or is your task to measure/observe this Vref/4 voltage?

BR

- - - Updated - - -

Shame on me, I just realized you are using a DAC and not an ADC.

Sry, for unnecessary reply.

Nevertheless, what is your intended application? Do you need an adjustable voltage or an constant accurate voltage of Vref/4 ?

Re: Design and implementation of sigma delta DAC

Thanks for the reply.
I need a constant voltage of Vref/4. This is used for the calibration of the ADC. I have been provided with voltage Vref and need to generate an voltage Vref/4 accurate to 15 bits. I didn't want to go for resistor string DAC or R-2R ladder. I am looking for accurate and simple configuration.

Re: Design and implementation of sigma delta DAC

What are your reference and desired Vref/4 voltage level?
There are a couple of single chip voltage references available [1] i.e. Vref = 5V and Vref/4 = 1.25 V.
With the stated specifications you can calculate your achievable resolution/ENOB.

[1] https://www.analog.com/media/en/technical-documentation/product-selector-card/vrefb.pdf

Re: Design and implementation of sigma delta DAC

Thanks for that. My Vref is 1.2 V and Vref/4 is 0.3V. I am thinking of building a circuit myself for this instead of using the available chips. Any lead on sigma delta DAC is much appreciated.

Re: Design and implementation of sigma delta DAC

Hi,

are you talking about IC_design or analog_circuit_design using ready to buy ICs?

Klaus

Re: Design and implementation of sigma delta DAC

It is IC design. I think i posted this in the wrong group. Basically i am trying to understand the working of sigma delta DAC to be able to design one for my requirements.

Hi,

now I moved the thread to "IC design" ...

****
I have no idea about IC design....

While a sigmal delta DAC is rather flexible, it is complex, too.

A rather precise 1/4 of input signal could be generated with: (precision is independent of resistor value and capacitor value of low pass filter)
* SPDT switch: NC to GND, NO to REF_input, COM to resistor (of RC lowpass)
* SPDT_control = PWM signal with exactly 1/4 duty cycle (should be easy to generate)
* low pass filter C: one pin to R (of COM) = output. Other pin to GND.

Notes:
SPDT charge injection will cause error in output signal, also ON_time_delay to OFF_time_delay mismatch.
Choose PWM frequency to get
* low charge injection error (the lower the frequency the better)
* low ouput ripple (the higher the frequency the better) (additional filter stages may improve ripple)

Don´t know if you can implement such a thing into your IC.

Klaus