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  1. #1
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    verilog 4:1 mux

    . Design a 4:1 mux in Verilog.

    Multiple styles of coding. e.g.
    Using if-else statements
    if(sel_1 == 0 && sel_0 == 0) output = I0;
    else if(sel_1 == 0 && sel_0 == 1) output = I1;
    else if(sel_1 == 1 && sel_0 == 0) output = I2;
    else if(sel_1 == 1 && sel_0 == 1) output = I3;

    Using case statement

    case ({sel_1, sel_0})
    00 : output = I0;
    01 : output = I1;
    10 : output = I2;
    11 : output = I3;
    default : output = I0;
    endcase

    1What are the advantages / disadvantages of each coding style shown above?
    2How Synthesis tool will give result for above codes?
    3What happens if default statement is removed in case statement?
    4What happens if combination 11 and default statement is removed?

    •   Alt19th May 2005, 13:42

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  2. #2
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    verilog mux

    1. one (if) has priority the other(case) has no
    2. case have full/parallel concept
    3. no impact to remove the default since the case is full case
    4. possible mismatch in gatelevel and rtl simulation.



  3. #3
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    priority mux verilog

    Hi, kxchorus,

    During simulation phase, remove the default statement may cause the unknow to spread.

    Good Luck



  4. #4
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    4:1 mux verilog

    u can read synopsys sold documents about DC.



    •   Alt20th May 2005, 06:52

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  5. #5
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    design a 4:1 mux in verilog

    using assign is better, it will not cause sim/synt mismatch.



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    case verilog

    If-else logic and case logic has different timing delay. Every possible condition should be outlined in combination logic block no matter if-else logic or case logic, Or else ,latch will be introduced.



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    4:1 verilog mux

    hi,

    if else can give you the priority type mux hardware while case statement will give you single mux.

    with regards,
    kul.



  8. #8
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    verilog if else simulate mux

    Multiple styles of coding. e.g.
    Using if-else statements
    if(sel_1 == 0 && sel_0 == 0) output = I0;
    else if(sel_1 == 0 && sel_0 == 1) output = I1;
    else if(sel_1 == 1 && sel_0 == 0) output = I2;
    else if(sel_1 == 1 && sel_0 == 1) output = I3;

    Using case statement

    case ({sel_1, sel_0})
    00 : output = I0;
    01 : output = I1;
    10 : output = I2;
    11 : output = I3;
    default : output = I0;
    endcase

    1What are the advantages / disadvantages of each coding style shown above?
    2How Synthesis tool will give result for above codes?
    3What happens if default statement is removed in case statement?
    4What happens if combination 11 and default statement is removed?


    Here there is no difference between the two codes, the output is the same, as well the priority is not taken into consideration in the above logic, prioritycomes under different conditions, when the above control signals are different, what i mean to say is when one statement is used for different select signal and the other used for different select signal then priority comes under picture.

    Here as u r mentioning all the the possibilities of the two signals that is 00, 01, 10, 11 then there is no difference, there is difference when u r using a full case and a parallel case

    hope it is understandable

    regards



  9. #9
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    4-1 mux and verilog

    after DC synthesis, same result will be generated.

    Quote Originally Posted by abhineet22
    . Design a 4:1 mux in Verilog.

    Multiple styles of coding. e.g.
    Using if-else statements
    if(sel_1 == 0 && sel_0 == 0) output = I0;
    else if(sel_1 == 0 && sel_0 == 1) output = I1;
    else if(sel_1 == 1 && sel_0 == 0) output = I2;
    else if(sel_1 == 1 && sel_0 == 1) output = I3;

    Using case statement

    case ({sel_1, sel_0})
    00 : output = I0;
    01 : output = I1;
    10 : output = I2;
    11 : output = I3;
    default : output = I0;
    endcase

    1What are the advantages / disadvantages of each coding style shown above?
    2How Synthesis tool will give result for above codes?
    3What happens if default statement is removed in case statement?
    4What happens if combination 11 and default statement is removed?



  10. #10
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    Re: code for 4:1 mux in verilog?tell the difference

    module MUX_4_1(
    input [3:0]i,
    input [1:0]s,
    output o
    );
    assign o= (s[0]==0)?((s[1]==0)?i[0]:i[1]):((s[1]==0)?i[2]:i[3]);

    endmodule



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