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if u have any constaint about area of core , then go to core limited design and vice versa. for more detail read M.J smith asic design and ASIC with SOC ,"author name i forgot".
both type of padding technique is related to area constaint for a chip and small power consumption also .
Pad limited design means your design has too many pads, so that the silicon area is not fully utilized. This is not cost-effective. To solve this, you either add function to your design or try to find IO lib with finer pad pitch, or use stacked pad, or flip-chip solution.
Core limited is the other way around. I believe most of the designs are core limited.
Core limited means the core logic area is the mosr section of the die.other way around. It is good for econimical.
Pad limited design means ur design has too many pads, so that the silicon is not fully utilized. This is not cost-effective. To solve this, you either add function to your design, just like test logic, or try to find IO lib with finer pad pitch, or use stacked pad, or flip chip solution.
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