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Insetion delay and Skew of the Clock

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sharu

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What if Insertion delay and Skew of Clock is way more than specified? What will happen to design?
 

As far as I know, it will make the timing convergence become harder....Hope this is helpful...;)
 

hi,
I think in most design , just care local skew.
 

Insertion delay is also very important because if u are trying to timing closure of a full ic then ok . but if u are closing lets say a module which will sit on a full ic . usally pll is used to make clock distribution ... see now what problem will come if you don't meet proper insertion delay !!!!
 

WHen synthesising , design maybe 10% overconstrained. you say it is far away.
I think , you'd better re-synthesis it to meet your time constraints.
 

If skew is larger, then data pass from one registe rto another register

will lost because of holding time violation.

if insertion delay is too large, The speed that your chip commnuicate with other

chip will be very slow.



sharu said:
What if Insertion delay and Skew of Clock is way more than specified? What will happen to design?
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