Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

can someone plz help with this verilog code of mine?

Status
Not open for further replies.
S

shakeebh

Member level 2
Joined
Apr 24, 2005
Messages
45
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
Pakistan
Activity points
1,852
removing sequential instance

Hello all

as some of u might remember, I discussed about making 16 bit RISC processor under another topic. Well this time the problem is that despite my best, I am unable to make interconnections among sub-modules in my main/top module RISC. I am using Xilinx ISE 6.1i, device spartan IIe, Modelsim SE 5.7g and coding is in verilog as the topic suggests it too. So can anyone plz solve the following two or at least one of two things for me:

1) Make interconnections between my modules. Earlier when I had this error (actually it appears as a warning when I synthesize), I dont know how but I knew, I had somehow removed them all! But this time this is not ready to go away that easily. So plz someone of you experienced enuff could tell me at least what the common problem usually is under these situations and how to go about debugging them coz i have tried all that I had even schematic editor but its been all in vain so far.

following is one of many such warnings:

WARNING:Xst:1291 - FF/Latch <memory_write_stage4_ir4_6> is unconnected in block <RISC>.

but I believe that I have connected them :S

2) The ALU module works fine in behavioral simulation but when I map it and do post-place and route simulation, it starts giving me XXXXXXXXXX values at one or two places. I tried to adjust the clock frequency but in a futile attemp thinking that decreasing it would coz the delays to settle down. Ofcourse you cannot fix this unless u know instruction set and its format (m i right?) but at the moment I only seek comments that what could cause such problems usually and how they can be circumvented coz I had thought before that making an ALU (simple at least) would be one of the simplest tasks :(

Looking forward to ur favorable response....

thanks in advance
 

16 bit risc verilog

Hi Shakeebh,
I have corrected the code, Plaese do the simulation and let me know if
ther are any errors!
 

error @posedge ps

thanks for the promp reply. I have noted the corrections u made and also ur comments in the ALU module. Rest i aint going through now coz i have to leave for the class. Unfortunately the error still persists. Following are the unusual warning/error messages generated by modelsim at the start post-place and route simulation

thanks again.......


# Loading alu_timesim.sdf
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
# Time: 0 ps Iteration: 0 Instance: /alu_test/UUT
# ** Error: I:/Xilinx/verilog/src/simprims/X_LATCHE.v(40): $setup( negedge I &&& in_clk_enable:407629 ps, negedge CLK:407897 ps, 304 ps );
# Time: 407897 ps Iteration: 0 Instance: /alu_test/UUT/result_8
# ** Error: I:/Xilinx/verilog/src/simprims/X_SFF.v(274): $setup( negedge I &&& (in_clk_enable == 1):1011482 ps, posedge CLK:1011683 ps, 304 ps );
# Time: 1011683 ps Iteration: 0 Instance: /alu_test/UUT/sync_result_13_180
# ** Error: I:/Xilinx/verilog/src/simprims/X_SFF.v(273): $setup( posedge I &&& (in_clk_enable == 1):1411413 ps, posedge CLK:1411681 ps, 304 ps );
# Time: 1411681 ps Iteration: 0 Instance: /alu_test/UUT/sync_result_4_176
# ** Error: I:/Xilinx/verilog/src/simprims/X_SFF.v(273): $setup( posedge I &&& (in_clk_enable == 1):1411443 ps, posedge CLK:1411681 ps, 304 ps );
# Time: 1411681 ps Iteration: 0 Instance: /alu_test/UUT/sync_result_6_178
# ** Error: I:/Xilinx/verilog/src/simprims/X_LATCHE.v(45): $width( posedge CLK:1604669 ps, :1605402 ps, 1250 ps );
# Time: 1605402 ps Iteration: 0 Instance: /alu_test/UUT/carry_0
# No errors or warnings
 

time: 0 ps iteration: 0 instance

Hi,
If these warnings/errors are coming while the reset is asserted them you can safely
ignore them. In your design if ur using flops without reset then you need to forcefully
initialize them to some random values. Last option is adujust ur clock frequency.
 

$setup( negedge i &&& (in_clk_enable1 == 1)

OK I will look along these lines. but could u help me with that blocks unconnected problem in my top module? I have synthesized it and its still as it was before.
 

alu behavioural simulation xilinx

The warning ur getting is because ur not using the output of some of the
flops and so they get optimised. You can ignore them. I tried synthesize ur
module with SynplifyPro and I got following warnings and they look OK!


Code: 
@W: risc.v(363): Removing sequential instance memory_write_stage4.ir4[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":363:3:363:9
@W: risc.v(363): Removing sequential instance memory_write_stage4.ir4[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":363:3:363:9
@W: risc.v(363): Removing sequential instance memory_write_stage4.ir4[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":363:3:363:9
@W: risc.v(363): Removing sequential instance memory_write_stage4.ir4[8] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":363:3:363:9
@W: risc.v(363): Removing sequential instance memory_write_stage4.ir4[7] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":363:3:363:9
@W: risc.v(363): Removing sequential instance memory_write_stage4.ir4[6] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":363:3:363:9
@W: risc.v(363): Removing sequential instance memory_write_stage4.ir4[5] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":363:3:363:9
@W: risc.v(363): Removing sequential instance memory_write_stage4.ir4[4] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":363:3:363:9
@W: risc.v(363): Removing sequential instance memory_write_stage4.ir4[3] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":363:3:363:9
@W: risc.v(363): Removing sequential instance memory_write_stage4.ir4[2] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":363:3:363:9
@W: risc.v(176): Removing sequential instance decode_instruction_stage2.ir2[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":176:3:176:9
@W: risc.v(176): Removing sequential instance decode_instruction_stage2.ir2[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":176:3:176:9
@W: risc.v(176): Removing sequential instance decode_instruction_stage2.ir2[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":176:3:176:9
@W: risc.v(176): Removing sequential instance decode_instruction_stage2.ir2[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":176:3:176:9
@W: risc.v(176): Removing sequential instance decode_instruction_stage2.ir2[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":176:3:176:9
@W: risc.v(176): Removing sequential instance decode_instruction_stage2.ir2[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":176:3:176:9
@W: risc.v(176): Removing sequential instance decode_instruction_stage2.ir2[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":176:3:176:9
@W: risc.v(176): Removing sequential instance decode_instruction_stage2.ir2[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":176:3:176:9
@W: risc.v(176): Removing sequential instance decode_instruction_stage2.ir2[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":176:3:176:9
@W: risc.v(176): Removing sequential instance decode_instruction_stage2.ir2[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":176:3:176:9
@W: risc.v(308): Removing sequential instance alu_stage3.ir3[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
@W: risc.v(308): Removing sequential instance alu_stage3.ir3[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
@W: risc.v(308): Removing sequential instance alu_stage3.ir3[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
@W: risc.v(308): Removing sequential instance alu_stage3.ir3[8] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
@W: risc.v(308): Removing sequential instance alu_stage3.ir3[7] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
@W: risc.v(308): Removing sequential instance alu_stage3.ir3[6] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
@W: risc.v(308): Removing sequential instance alu_stage3.ir3[5] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
@W: risc.v(308): Removing sequential instance alu_stage3.ir3[4] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
@W: risc.v(308): Removing sequential instance alu_stage3.ir3[3] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
@W: risc.v(308): Removing sequential instance alu_stage3.ir3[2] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
@W: risc.v(308): Removing sequential instance alu_stage3.psw[3] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
@W: risc.v(308): Removing sequential instance alu_stage3.psw[2] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
@W: risc.v(308): Removing sequential instance alu_stage3.psw[1] of view:UNILIB.FDR(PRIM) because there are no references to its outputs  @W:"h:\tmp\risc.v":308:3:308:9
 

    S

    shakeebh

    Points: 2
    Helpful Answer Positive Rating
I have the same problem .. but I can't ignore simply because the synthesis optimizes my circuit and doesn't map my RTL to the target device technology library .. and finally, the netlist doesn't contain anything except the top level interface !!!!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top