design D flip flop with calculate basic timing of it,such as setup and hold time

hi friends

how can i design a D flip flop and calculate setup and hold time for it?
Is there possible design d flip flop with PSSL family of logic ?

thanks in advanced

these are basic concepts of digital logic. have you tried googling or reading some material?

hi
yes, I know what is the basic timing's flip flop. but I want a transistor implementation of special flip flop that clearly be mentioned technology (ie 180 nm) and setup and hold time. I want write sub circuit D flip flop in hspice and use that as register between pipeline stages. and because of that I have to know setup and hold time of flip flop that I use.

Would you please tell me about it?

fateme_ayat said:

hi
yes, I know what is the basic timing's flip flop. but I want a transistor implementation of special flip flop that clearly be mentioned technology (ie 180 nm) and setup and hold time. I want write sub circuit D flip flop in hspice and use that as register between pipeline stages. and because of that I have to know setup and hold time of flip flop that I use.

Would you please tell me about it?

Click to expand...

sorry, your english is really hard to understand. I *think* you have some schematic idea of a flop design and you don't know how to turn that into layout. is that the case?

hi
I'm very sorry.I try explain my problem better.
I should design a pipelined adder . In order to obtain frequency of this adder I should know setup and hold time of registers that put between stages :
[ Tclk >= (dmax - dmin) +ts +th +2tskew ]

this is clock period of "mesochronous pipelining" from this article:
"Tatapudi, Suryanarayana B., and José G. Delgado-Frias. "A mesochronous pipelining scheme for high-performance digital systems." IEEE Transactions on Circuits and Systems I: Regular Papers 53.5 (2006): 1078-1088."

I wrote h-spice code for this adder, and I try several implementation of D flop (such that master slave), but I don't know value of setup and hold time, and I don't want calculate these values myself.

what I want is that an implementation of d flop that i know every thing about it(i.e schematic, setup time, hold time, clock-to-Q time) . And also I want to know that, can I use PSSL family of logic to achieve best performance for registers?

I appreciate your help.