Questions on packaging and testing of LDO

Hi All,

I've just taped-out an LDO, and I'm going to package and test the LDO soon. I have several doubts about my subsequent work. I greatly appreciate your kind suggestions and advises.

Before I raise my questions, please first have a glance of some specifications of the LDO,

Input voltage:1.2V
Output voltage:1V
Max loading current: 200mA
Output capacitor: ~uF
Primary measurement parameters: PSRR, transient response, etc.

Below are my doubts/questions:

1. What type of package should I choose, (DIP or QFN or others)? It seems that the long bonding wire of DIP and the resultant parasitic inductance may degrade the performance of the LDO.
2. Should I solder the chip to the PCB (though expensive, the cost is not a big issue for my project) or should I use a socket? It seems that the socket brings high parasitic inductance. However, if I choose to solder the chip to the PCB, I'm afraid that the thermal issue may damage/stress my chip.
3. What kind of circuit should I adopt to emulate the loading, (resistor or current source or others)?
4. Any rule-of-thumb for the pertinent PCB design (e.g., the placement of the element, etc.)?

Looking forward to your reply.

Thank you in advance.

Bond wire inductance is probably not a problem
unless you are trying to make a LDO which can
follow extremely high dI/dt on the supply-input
path. But usually this job is assigned to the output
filter capacitor which is more suited to the job.
A "cap free" LDO would care more.

Bond wire resistance is a real thing and at 200mA
could amount to tens of mV error. Hopefully you
designed it with Kelvin feedback (its own pad, which
would be bonded to the output posts so as to see
the pin voltage and not an internal point which
puts the bond wires and package leadframe outside
the feedback loop).

DIPs are crappy. You should be able to get good
test contactors for QFN, or small outline packages.
The same I*R issues apply to test hardware, from
the other end, and you want Kelvin force/sense
pairs on anything high current. Zero insertion force
DIP sockets don't give this generally. Custom pogo-
pin test sockets are nice (and $$$) but you may not
be able to fit two pogos on a QFN pad. Chase down
some high-end test socket vendors and see. I
forget now, the one we liked best where I last
worked.

Soldering to an eval board is a way to go, for small
quantities may cost less than a good socket (you
can connectorize boards for harness Kelvin
connection). Also lets you put decoupling closer-in
physically and electrically than a socketed test
solution. You can also consider, for preliminary
validation, chip-on-board (chip bond-wired to gold
lands, similar to package cavity geometry, but
with no encapsulation or with "glob-top". Not good
for environmental testing or careless handling, but
cheap and quick, and perhaps the board has future
uses in engineering lab.

0.2V times 0.2A is not much power to worry about.

You want to have a step-load capability to assess
the dynamic response.