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    How to convert vhdl behavioral test bench to synthesized test bench for validation

    Hello,

    I have tested my DUT in simulation using VHDL test bench. The test bench has behavioral coding.
    I want to use the same test bench for validation on FPGA. So the test bench needs to be synthesizable.

    My query: Are there any other standard tools from vendors (like synopsys, cadence...) which can automatically
    converts the behavioral test bench to synthesizable?

    or Are there any scripts available to do so?

    Thanks in advance!

    •   Alt14th March 2017, 11:05

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    Re: How to convert vhdl behavioral test bench to synthesized test bench for validatio

    Generally speaking why would someone want to write a test-bench that will go into implementation (ASIC/FPGA doesn't matter)? I would question that design in the first place.

    I have tested my DUT in simulation using VHDL test bench. The test bench has behavioral coding.
    I want to use the same test bench for validation on FPGA. So the test bench needs to be synthesizable.
    You need to decide which part of your design is going to be synth and implemented on the FPGA/ASIC. That part of the design needs to be written using behavioral coding for synthesis. Anything other than that can remain in the test-bench.

    Ok there are times when one desires to have a synthesizable test-bench (e.g.- a pattern-generator or something like that) that can feed data to the DUT. In such a situation I would package such a patter-generator inside the DUT itself. In such a case just write the behavioral RTL coding for that particular module that can be synthesized (e.g.- Don't use 'wait statements' and stuff like that).

    My query: Are there any other standard tools from vendors (like synopsys, cadence...) which can automatically
    converts the behavioral test bench to synthesizable?

    or Are there any scripts available to do so?
    In my knowledge, no.
    Last edited by dpaul; 14th March 2017 at 12:25.
    .....yes, I do this for fun!



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    Re: How to convert vhdl behavioral test bench to synthesized test bench for validatio

    The answer to this is yes and no.
    For HDL testbenches, the answer is No, you cannot do this. The code will contain software like concepts that will not map to hardware.

    But - some tools like simulink allow hardware in the loop testing, where you use the same code in both your simulink model and on the hardware.

    The problem here is a question of drivers. When you test on hardware, you need to somehow get data into the board to pass through your design. In Simulink's case it builds your FPGA with additional ethernet or PCIe cores, and Matlab contains the drivers to transfer the stimulus from Simulink to the board.

    Then you go all the way to ASIC emulation using many FPGAs - but you wont be using the same HDL tests - you will have specially designed tests.



    •   Alt14th March 2017, 13:04

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    Re: How to convert vhdl behavioral test bench to synthesized test bench for validatio

    Hello dpaul,

    Thanks a lot for reply.
    The motivation to do is to speed up the verification of DUT(RTL design). I got 2-3 research papers people worked on the automation of this process

    http://citeseerx.ist.psu.edu/viewdoc...=rep1&type=pdf

    http://ieeexplore.ieee.org/document/4669307/

    Seeing these papers, I was expecting some scripts/tools should be available. But could not find it.



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    Re: How to convert vhdl behavioral test bench to synthesized test bench for validatio

    Seeing these papers, I was expecting some scripts/tools should be available. But could not find it.
    There is always a substantial time lag between what is done in research and what is is being done in the industry.

    I think for the time being to get your TB to synthesize, write its RTL accordingly.
    .....yes, I do this for fun!



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    Re: How to convert vhdl behavioral test bench to synthesized test bench for validatio

    Those papers seem heavy on theory and light on any real content. Also, what code examples there are are very simplistic. It appears they would only support the very simplest of test benches that use absolute delays/wait statments. I guess it would utterly fail when you get into anything more complicated - like randomised delays etc. then when you talk about transaction driven testbenches - just forget about it.

    Basically - these papers seem to focus on testbenches people read in text books. Anything done in industry is not covered.



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    Re: How to convert vhdl behavioral test bench to synthesized test bench for validatio

    Dear TrickyDicky, dpaul,

    I really appreciate you went through papers and gave your feedback.
    Even I acknowledge that it is difficult to cover all the possible testbench scenarios.
    So I thought if some script or tool is available, I can try to modify it and mature it.

    Conclusion:
    It is not good idea to spend time to automation scripts.
    I should manually design synthesize test bench , if i want to validate DUT on FPGA



    •   Alt17th March 2017, 06:37

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    Re: How to convert vhdl behavioral test bench to synthesized test bench for validatio

    Quote Originally Posted by nainathakur1121 View Post
    Dear TrickyDicky, dpaul,

    I really appreciate you went through papers and gave your feedback.
    Even I acknowledge that it is difficult to cover all the possible testbench scenarios.
    So I thought if some script or tool is available, I can try to modify it and mature it.

    Conclusion:
    It is not good idea to spend time to automation scripts.
    I should manually design synthesize test bench , if i want to validate DUT on FPGA
    Essentially, yes.

    I have had good luck with NiDAQ products that have FPGAs embedded in them. I can take a synthesisable testbench, modify a few things, and start running it on the FPGA that is then connected to my circuit. I can control the whole operation using matlab too. It looks neat.



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