oAwad
Full Member level 2
Hello All,
I designed a layout in SoC Encounter using NangateOpenCellLibrary 45nm which had zero geometry and connectivity violations. I then exported GDS file and verilog netlist from Encounter. I went to Calibre to run LVS and afterwards PEX for post-layout simulations.
Here are my steps:
1) run v2lvs command "v2lvs -v netlist_encounter2.v -l NangateOpenCellLibrary.v -o netlist_v2lvs.spi -s NangateOpenCellLibrary.spi -s1 VDD -s0 VSS"
2) I open calibre -gui, attach GDS and spice netlist (from v2lvs) and everything as default....then hit Run LVS.
I then get these errors (below is part of the LVS summary report)
NOTE: maybe the problem is with LVS setup, but I can't say as my experience is little with Calibre.
I get these .SUBCKT issues and layout shorts (I don't know if these layout shorts are problems)
I didn't set any initial correspondence points, but I found in the LVS summary report that there are correspondence points set by default. BUT they don't include all my I/O ports, can this be causing these errors ? (see code below)
If I should set initial correspondence points including all my I/O ports, please tell me how to set it as I don't have experience with Calibre.
I designed a layout in SoC Encounter using NangateOpenCellLibrary 45nm which had zero geometry and connectivity violations. I then exported GDS file and verilog netlist from Encounter. I went to Calibre to run LVS and afterwards PEX for post-layout simulations.
Here are my steps:
1) run v2lvs command "v2lvs -v netlist_encounter2.v -l NangateOpenCellLibrary.v -o netlist_v2lvs.spi -s NangateOpenCellLibrary.spi -s1 VDD -s0 VSS"
2) I open calibre -gui, attach GDS and spice netlist (from v2lvs) and everything as default....then hit Run LVS.
I then get these errors (below is part of the LVS summary report)
NOTE: maybe the problem is with LVS setup, but I can't say as my experience is little with Calibre.
Code:
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of ports.
Error: Different numbers of nets.
Error: Different numbers of instances.
Error: Connectivity errors.
Error: Property errors.
Warning: Ambiguity points were found and resolved arbitrarily.
Warning: LVS property resolution maximum exceeded.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT aes_cipher_top aes_cipher_top
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
LVS COMPONENT TYPE PROPERTY element
LVS COMPONENT SUBTYPE PROPERTY model
// LVS PIN NAME PROPERTY
LVS POWER NAME "VDD"
LVS GROUND NAME "VSS"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES NO
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE NO
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS NO
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 32
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Reduction
LVS REDUCE SERIES MOS YES
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS YES
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Trace Property
TRACE PROPERTY mn(nmos_vtl) l l 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_vtl) w w 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_vtl) l l 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_vtl) w w 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_vth) l l 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_vth) w w 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_vth) l l 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_vth) w w 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_vtg) l l 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_vtg) w w 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_vtg) l l 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_vtg) w w 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_thkox) l l 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_thkox) w w 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_thkox) l l 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_thkox) w w 4e-09 ABSOLUTE
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of ports (see below).
Error: Different numbers of nets (see below).
Error: Different numbers of instances (see below).
Error: Connectivity errors.
Error: Property errors.
Warning: Ambiguity points were found and resolved arbitrarily.
Warning: LVS property resolution maximum exceeded.
LAYOUT CELL NAME: aes_cipher_top
SOURCE CELL NAME: aes_cipher_top
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 11268 390 *
Nets: 42826 42747 *
Instances: 41746 41746 MN (4 pins)
41746 41746 MP (4 pins)
------ ------
Total Inst: 83492 83492
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 11268 390 *
Nets: 16215 16112 *
Instances: 1899 1691 * MN (4 pins)
1333 1309 * MP (4 pins)
180 180 OAI_3_3 (7 pins)
977 977 SPDW_2_1 (4 pins)
280 280 SPDW_2_1_1 (5 pins)
631 631 SPDW_2_2 (5 pins)
360 360 SPDW_2_2_1 (6 pins)
120 120 SPDW_2_2_2 (7 pins)
1283 1283 SPUP_2_1 (4 pins)
301 301 SPUP_2_1_1 (5 pins)
440 440 SPUP_2_2 (5 pins)
620 620 SPUP_2_2_1 (6 pins)
160 160 SPUP_2_2_2 (7 pins)
1609 0 * _invb (6 pins)
3327 4936 * _invv (4 pins)
87 87 _invx2v (4 pins)
1368 0 * _nand2b (7 pins)
451 1819 * _nand2v (5 pins)
524 0 * _nand3b (8 pins)
80 604 * _nand3v (6 pins)
242 242 _nand4v (7 pins)
448 0 * _nor2b (7 pins)
920 1368 * _nor2v (5 pins)
430 0 * _nor3b (8 pins)
32 462 * _nor3v (6 pins)
181 181 _nor4v (7 pins)
285 0 * _pdw2b (5 pins)
18 407 * _pdw2v (4 pins)
282 0 * _pup2b (5 pins)
0 294 * _pup2v (4 pins)
3467 0 * _sdw2b (5 pins)
2837 6304 * _sdw2v (4 pins)
3174 0 * _smp2b (5 pins)
2545 5719 * _smp2v (4 pins)
------ ------
Total Inst: 30891 30775
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net VDD VDD
-------------------------- --------------------------
** missing connection ** XU1352/M_i_42:b
** missing connection ** XU1344/M_i_42:b
** missing connection ** XUI get these .SUBCKT issues and layout shorts (I don't know if these layout shorts are problems)
I didn't set any initial correspondence points, but I found in the LVS summary report that there are correspondence points set by default. BUT they don't include all my I/O ports, can this be causing these errors ? (see code below)
If I should set initial correspondence points including all my I/O ports, please tell me how to set it as I don't have experience with Calibre.
Code:
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 390 390 10878 0
Nets: 4239 4239 11976 11873
Instances: 640 640 1259 1051 MN(NMOS_VTL)
0 0 1333 1309 MP(PMOS_VTL)
74 74 106 106 OAI_3_3
310 310 667 667 SPDW_2_1
20 20 260 260 SPDW_2_1_1
167 167 464 464 SPDW_2_2
23 23 337 337 SPDW_2_2_1
47 47 73 73 SPDW_2_2_2
890 890 393 393 SPUP_2_1
26 26 275 275 SPUP_2_1_1
29 29 411 411 SPUP_2_2
24 24 596 596 SPUP_2_2_1
37 37 123 123 SPUP_2_2_2
0 0 1609 0 _invb
3327 3327 0 1609 _invv
87 87 0 0 _invx2v
0 0 1368 0 _nand2b
451 451 0 1368 _nand2v
0 0 524 0 _nand3b
80 80 0 524 _nand3v
242 242 0 0 _nand4v
0 0 448 0 _nor2b
920 920 0 448 _nor2v
0 0 430 0 _nor3b
32 32 0 430 _nor3v
181 181 0 0 _nor4v
0 0 285 0 _pdw2b
18 18 0 389 _pdw2v
0 0 282 0 _pup2b
0 0 0 294 _pup2v
0 0 3467 0 _sdw2b
2837 2837 0 3467 _sdw2v
0 0 3174 0 _smp2b
2545 2545 0 3174 _smp2v
------- ------- --------- ---------
Total Inst: 13007 13007 17884 17768
o Statistics:
25 source nets were deep shorted to 1.
302 layout mos transistors were reduced to 134.
168 mos transistors were deleted by parallel reduction.
302 source mos transistors were reduced to 134.
168 mos transistors were deleted by parallel reduction.
160 nets and 262 instances were matched arbitrarily.
o Layout Names That Are Missing In The Source:
Ports: SA01[0] N715 W0[18] N228 N413 SA00[4] N194 N48 N1392 N671 N360 N394 N657 N687
N678 N383 N674 N659 N174 N102 N919 N240 N535 N540 N242 N545 N483 N408 N550 N574
N1484 N258 N576 N563 N557 N415 N1523 N412 N1485 N250 N252 N1459 N710 N377 N388
N184 N664 N695 N769 N682
o Initial Correspondence Points:
Ports: VDD VSS KEY[124] TEXT_IN[112] TEXT_IN[16] TEXT_IN[22] KEY[117] TEXT_IN[118]
TEXT_IN[115] TEXT_IN[114] TEXT_IN[17] TEXT_IN[91] TEXT_IN[90] TEXT_IN[72]
TEXT_IN[74] KEY[76] KEY[16] TEXT_IN[41] TEXT_IN[101] TEXT_IN[106] TEXT_IN[108]
TEXT_IN[125] TEXT_IN[97] TEXT_IN[10] KEY[66] KEY[2] KEY[61] KEY[77] KEY[34]
TEXT_IN[63] KEY[27] TEXT_IN[2] KEY[102] KEY[96] KEY[60] TEXT_IN[61] TEXT_IN[13]
TEXT_IN[6] KEY[5] KEY[67] KEY[32] TEXT_OUT[82] TEXT_OUT[87] TEXT_OUT[17]
KEY[125] TEXT_OUT[22] TEXT_OUT[16] TEXT_OUT[49] TEXT_OUT[21] KEY[122]
Nets: SA01[0] N715 W0[18] N228 N413 SA00[4] N194 N48 N1392 N671 N360 N394 N657 N687
N678 N383 N674 N659 N174 N102 N919 N240 N535 N540 N242 N545 N483 N408 N550 N574
N1484 N258 N576 N563 N557 N415 N1523 N412 N1485 N250 N252 N1459 N710 N377 N388
N184 N664 N695 N769 N682
o Ambiguity Resolution Points:
(Each one of the following objects belongs to a group of indistinguishable objects.
The listed objects were matched arbitrarily by the Ambiguity Resolution feature of LVS.
Arbitrary matching may be prevented by assigning names to these objects or to adjacent nets).
Layout Source
------ ------
Nets
----
X4/1633 Xu0/Xr0/Xout_reg_24_/QN
X4/1626 Xu0/Xr0/Xout_reg_30_/QN
X4/X6511/14 Xld_r_reg/z10
X7/X4986/14 Xdcnt_reg_2_/z10
X4/X6511/13 Xld_r_reg/z9
X7/X4986/13 Xdcnt_reg_2_/z9
X4/X6511/10 Xld_r_reg/z3
X7/X4986/10 Xdcnt_reg_2_/z3
X4/X6503/10 Xu0/Xw_reg_0__24_/z3
X3/X8048/10 Xu0/Xw_reg_0__25_/z3