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    Failing Timequest path not shown in RTL viewer

    Hello,

    I'm using a 128 to 32 bit FIFO in my Altera Cyclone V SOC design.
    Timequest shows a setup violation on 10 lines internal to this IP.
    The "Launch Clock" and "Latch Clock" for the failing paths are the same.

    However, for some reason I can't locate the failing paths in the RTL viewer.
    As if they don't really exist...

    What's going on?

    •   Alt9th March 2017, 09:49

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    Re: Failing Timequest path not shown in RTL viewer

    They may not exist in the RTL viewer.
    Try the technology map view.


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    •   Alt9th March 2017, 10:12

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    Re: Failing Timequest path not shown in RTL viewer

    It's not there either...



    •   Alt13th March 2017, 16:23

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    Re: Failing Timequest path not shown in RTL viewer

    Start looking for blah, blah, blah, removed due to x, y, z begin static type stuff in the reports.

    Or if you really want whatever it is to stick around start adding keep and preserve attributes to those signals.

    - - - Updated - - -

    Opps, I just noticed you aren't looking for paths you already know exist but are trying to find one that magically appears.

    What does this path look like, can you find it in a netlist of the design?


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  5. #5
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    Re: Failing Timequest path not shown in RTL viewer

    Opps, I just noticed you aren't looking for paths you already know exist but are trying to find one that magically appears.
    Correct.

    It's an ALTERA IP - a ratio changing (128 to 32 bits) FIFO.
    The failing net is of a RAM block this FIFO uses.
    can you find it in a netlist of the design?
    Good idea, I'll look.

    - - - Updated - - -

    I suspect these are nets that have been optimized away - yet remain in TimeQuest due to a bug.



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