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layout of digital input buffer??

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junsik

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Hi, I would like to know the schematic and function of the layout shown in the below figure. Briefly.
it is probably an input buffer of CMOS logic circuit. But it seems to be slightly different from the MOS device I know.
What is it? please let me know.

Thank you.
IC_input_buffer.jpgMOS_IC.png
 

Isn't it a standard CMOS input? ESD protection and 2 inverters in series, i.e. inverting & non-inverting input:

 
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    junsik

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Looks a bit "busy" to be just an input buffer, but it
could be that it's a general purpose bidirectional pad
call configured as an input. Then you have the output
buffer circuitry as well, tri-stated under logic control
(or tied off to rail at the output enable pin).

Some logic families were done "mini-array" style and
every signal pad was a general purpose I/O cell, mask
personalized at top (or sole) metal level.
 
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    junsik

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I attached the detailed layout. The bottom part is definitely MOS, but i don't know what the part on the top meas. What is it??? it is an input stage of inverter.

tt.jpg

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Um... thank you, please look at the relpy below. I attached the detailed layout
 

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