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Dummies requirement in 40 nm process

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hetirajhimanshu

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Hi guys I am designing the layout of a a differential amplifier in cadence virtuoso layout xl and technology node is 40 nm. This reqyuires matching of two nmos devices. suppose i made an array of 4x4 to macth two nmos devices, then according to the rule of 40 nm global foundries, how many dummy layers surrounding the main device should i need ?
 

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