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When is the VHDL pointer useful?

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matrixofdynamism

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I know that pointers exist in VHDL and somehow the file IO functions make use of them also. It is also possible to dynamically allocate memory and free it when using pointers like we do in C++. However, since VHDL only describes hardware and this pointer code will only be nonsynthesizeable anyway, I am curious to know how people find this VHDL feature useful useful.
 

I know that pointers exist in VHDL and somehow the file IO functions make use of them also. It is also possible to dynamically allocate memory and free it when using pointers like we do in C++. However, since VHDL only describes hardware and this pointer code will only be nonsynthesizeable anyway, I am curious to know how people find this VHDL feature useful useful.

In testbenches...
 

I know that pointers exist in VHDL and somehow the file IO functions make use of them also. It is also possible to dynamically allocate memory and free it when using pointers like we do in C++. However, since VHDL only describes hardware and this pointer code will only be nonsynthesizeable anyway, I am curious to know how people find this VHDL feature useful useful.

I found it very usefull making a model of a massive interconnected MUX, with the link tables and packet queue models all built with linked lists.
And sparse memory array models...
Loading files without knowing their size beforehand (ie. read the header and dynamically allocate the array for it)...
And in VHDL 2008 you can even build a generic linked list type to accept any type.

(non-synthesisable, testbench) List goes on...
 

Well folks, I knew it would be used in testbenches but could not think of a scenario so I posted a question here so that industry veterans could provide an insight into this aspect of VHDL. TrickyDicky, I find the examples you give quite interesting though I also think that SystemVerilog may perhaps by more suitable for doing things like that, that is only my assumption though
 

Well folks, I knew it would be used in testbenches but could not think of a scenario so I posted a question here so that industry veterans could provide an insight into this aspect of VHDL. TrickyDicky, I find the examples you give quite interesting though I also think that SystemVerilog may perhaps by more suitable for doing things like that, that is only my assumption though

Yes, SV is more suitable and re-use is easy in SV.
But thats not to say it cannot be done in VHDL. A lot of what you can do in SV can be done in VHDL.
 

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