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  1. #1
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    Manual modification on layout generated by SoC encounter

    Hello,

    I have a layout design in SoC encounter to which I want to add manually some extra wires to the layout (these are EXTRA and don't have anything to do with the design netlist) and modify the gap between another some wires (to measure coupling capacitance and crosstalk effects between wires). I'm using NanGate 45nm Open Cell Library.

    I'm beginning my design using LEF files.

    My questions are:

    - Can I do this modification in SoC encounter or I have to go for Virtuoso ?

    - If Virtuoso, what is the best format to export my design (GDS or OA) ? and how ? (Please provide detailed description)

    - I want to know if there is a difference between parasitic extraction in Virtuoso and encounter. (Which is better in analyzing coupling capacitance between interconnect wires) ?

    Thanks

    •   Alt15th February 2017, 19:48

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  2. #2
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    Re: Manual modification on layout generated by SoC encounter

    a) yes, you can draw wires freely using both the gui and commands
    b) doesn't matter
    c) encounter has multiple built-in capacitance extraction modes, some are simple, some are complicated. virtuoso is kind of the same. I would decide based on the design size.


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    •   Alt16th February 2017, 00:34

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  3. #3
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    Re: Manual modification on layout generated by SoC encounter

    Thanks for your reply

    When a draw an extra wire, it is assigned to the net next to it. I want to a assign a new net for it (which is not included in the netlist) so in order to be able to measure the crosstalk between two different nets.

    My layout is an AES encryption core of 27332 gates. So what is the best RC extraction mode to use ?

    Also, I would like to know how SoC encounter generate its DRC rules from LEF files and how to change it if I want to decrease the distance between two wires beyond the min. distance.

    Thanks



    •   Alt17th February 2017, 11:32

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  4. #4
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    Re: Manual modification on layout generated by SoC encounter

    Quote Originally Posted by oAwad View Post
    Thanks for your reply

    When a draw an extra wire, it is assigned to the net next to it. I want to a assign a new net for it (which is not included in the netlist) so in order to be able to measure the crosstalk between two different nets.

    My layout is an AES encryption core of 27332 gates. So what is the best RC extraction mode to use ?

    Also, I would like to know how SoC encounter generate its DRC rules from LEF files and how to change it if I want to decrease the distance between two wires beyond the min. distance.

    Thanks
    you can draw wires freely in Encounter. Just change the drawing mode. Or even better, learn what the command is to draw wires. You can assign a net name to it by going into it's properties.

    You will have to read about different extraction modes inside Encounter. If you want accuracy you will do sign-off extraction. If you want fast execution time, you will do simple RC lookup table type of extraction using QRC.

    You can edit LEF files, it's just a textual format. Look for metal layer definition, then edit the pitch field. Just bare in mind that the LEF is a subset of the real rules. Passing DRC in Encounter doesn't mean you are DRC clean.


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