Making inductor with Cadence layout editor

How can I make an inductor in cadence layout and simulate it ??? Do you have any guides ?

1) I know how to make inductor but I dont know how to simulate.

2) I am not talking about inductors in library. I want to make my own inductor.

Thank you.

You could copy a simulation model of a library inductor to a new name, and try and adapt its parasitics to those of your own inductor, which you can perhaps get from an RLC extraction?

when I flat the inductor it gives LVS error.

Ata_sa16 said:

when I flat the inductor it gives LVS error.

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Sure. As I told you above: you should try and take over the extracted parasitics (from the extracted layout view) into your schematic view.

As long as your inductor cell isn't yet flattened, you might be able to simply copy its extracted layout (i.e. its backannotated parasitics into schematic) to your inductor cell schematic.

I know what are you talking about. But I dont know how to do that.

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Let me explain my problem here:

I have an inductor with n=0.5 and W=30um.

When I set these values in the inductor which is defined in RF library it gives error that W cant be 30um when n=0.5.

So I want to edit the layout, increase W to 30um and simulate the inductor to see which value I obtain.



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Can you tell me how can I take over the extracted parasitics from the extracted layout view into my schematic view.

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I changed it like this.

Ata_sa16 said:

I know what are you talking about. But I dont know how to do that.
...
Can you tell me how can I take over the extracted parasitics from the extracted layout view into my schematic view.

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Dear, it's long ago when I used Cādence tools, and I don't even know which tool you're using for extraction (and LVS). Calibre, the Mentor tool, I guess.

I used to run Assura or Diva, and with these tools it was possible to back-annotate the extracted parasitics from the extracted layout view into the schematic view, which you then could save as your "real" schematic view - and the LVS then obviously would succeed because of the 1:1 compliance.

I think Calibre should have the same possibility of back-annotation. Try and search for it.

May be dick_freebird's post in a different inductor thread could be helpful for you. Good luck!

erikl said:

I used to run Assura or Diva, and with these tools it was possible to back-annotate the extracted parasitics from the extracted layout view into the schematic view, which you then could save as your "real" schematic view - and the LVS then obviously would succeed because of the 1:1 compliance.

Click to expand...

I am using assura but I do not understand what are you talking about. ;D

Ata_sa16 said:

I am using assura but I do not understand what are you talking about. ;D

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Check the options for back-annotation into the schematic view!