Vth vs L and gate leakage current

Hi everyone,
I have 32nm level 54 Nmos model. I want to simulate the change of threshold voltage accroding to channel length in LTspice but I do not know how. When I make dc op, it does not show Vth directly. with linear extrapolation technique, Vth can be found but it does not still show Vth directly so how can I simulate Vth vs L ?
Also wondering how can I calculate the gate leakage current. If Vds=0V and Vgs is swept 0 to Vdd, can we say that I(g) equals the gate leakage current?
Thank you.

Derun93 said:

... wondering how can I calculate the gate leakage current. If Vds=0V and Vgs is swept 0 to Vdd, can we say that I(g) equals the gate leakage current?

Click to expand...

Yes, the total gate current: the sum of Igs+Igb+Igd .

LTSpice may not be the best tool for this.

If you want to do it like device engineers do it, you
would set up to pull I(D) from two different points of
Vgs, and do the math. Or you could put two FETs at
two different voltages. Whether you prefer VTlin or
VTsat is your call. VTlin eliminates some of the
short channel's effects (lambda / Early voltage)
but VTsat would show more of the effect you are
asking about. Pick Vgs voltages above VT (like,
say, 0.7V and 0.8V if model card VT is 0.6V).
The extrapolated voltage where I(D) would be
zero, 2-point fit, is your VT. Make L a simulator
variable and loop it.

Now it could be easier to set things up as a rack
of FETs with Vg=0, Vd={whatever} and each gets
a current source (sink) on the S terminal that is
(say) 1uA*W/L. Neglecting all of the geometry
delta {W, L} action, this will put every FET at
a -(VT1uA) voltage. Of course at 32nm the deltas
matter a whole lot. But I'm not convinced LTSpice
is really caring about the same things that an
integrated circuit design oriented simulator does,
it's for discrete FETs and behavioral models mostly.

- - - Updated - - -

Real gate leakage current is a thing in very thin gate
dielectrics. Whether the model has any grasp of it or
any realism, is a question. The value in a single minimum
device may be below what the simulator tolerances are,
so results may be unreasonable.

You really probably only care about two cases, "on"
and "off", because dynamic gate current (gate dV/dt
onto Cox, and drain dV/dt across Cgd) will probably
dwarf it in circuits with dense transitions.

I would expect the gate current to be highest in the
"on" state because that puts field across the entire
gate area while "off" only applies fringing field from
the gate, and this is stood off by the LDD and spacer
by design to some extent. So maybe just put full VDD
on a 10x10 or 100x100 device and see if anything is
flowing in the VG supply (.OP). Or better yet, two
devices of grossly different size, and see if the model
gives you any difference in the two gate supplies.