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To shift half clock data

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To shift data half clock cycle before

Hi,
Is there any way to shift the data coming on rising edge clock, half cycle before in VHDL? I tried with falling edge instead of rising edge but unfortunately it didn't produce the result.

Code: 
shift_halfclk:process(clk) 

begin
 if falling_edge(clk) then
          data_half_shifted <= data;
  end if;     
end process;
 

Shift before? The statement is of course delaying the input data by a half clock cycle, related to a sampling clock working on rising_edge.
 

Hi,

first you need a timing diagram.
* input: data and clock
* output: data (and clock if modified)

Klaus
 

Is this for a testbench, or an FPGA?
if a testbench, then the answer is yes.

If on the FPGA, then this kind of thing would be done in the IO delay in the timing specifications, not RTL.
 

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