syncronize output signal

Hi,
i've to generate 2 sinusoidal signal (70Hz) in phase.
The problem is that those signals are generated by 2 altera nco on different fpga.

There is a 10Hz sync signal available

Thanks



How could i use that sync signal in order to put in phase two sinusoid or to correct the phase during normal operation?

Could you help me

Hi,

I assume the NCO output controls some kind of phase register (representing sine wave 0...360°).

You have to define one FPGA as master..clearing phase registers of both FPGAs at the same time.

Klaus

Altera NCO has a phase input register and only clearing that register doesn't correct the phase of output signal.

What does the sync signal signify? I assume it must signal some point in the phase of the NCO output that is consistent otherwise it's worthless for syncrhonizing the two NCOs.

If the sync signal is always output on a specific NCO value then you could conceivably just let the second NCO run until it reaches the value or perhaps the one before that value (to allow for pipelining the synchronization). Once it reaches that value disable that NCO using the clock enable. Now all you need to do is wait for the next sync and enable the NCO and it should be in sync.

Note this might only work if the NCO is clocked with some multiple of the NCO output frequency as otherwise the lower order bits of the output at the sync point may vary, but you can compensate for this by perhaps using some averaging algorithm to determine where to generate the enable. You'll also have to make sure you stop the NCO at the correct point in the phase, so it will start up in phase instead of say 180 degrees out of phase (for zero crossing). If the sync is lined up with anything other than the peak (+ or -) then there is at least 2 points that are identical but out of phase.

The problem isn't fully specified. One interesting point is if both FPGAs have a common clock source or individual crystal generators.
In the former case, both NCOs will maintain a fixed phase relation once they have been started, presumed they use the same frequency setting. So the problem reduces to start both NCOs simultaneously, as discussed by ads-ee.

In the latter case, both NCO outputs will slowly drift apart if they are not periodically synchronized. My favorite solution for similar situations is to synchronize either one PLL output or all PLL outputs of slave FPGAs with a master FPGA clock by using the dynamic phase shift feature of Altera PLLs. Frequency differences of several 100 ppm can be compensated this way, the typical crystal accuracy is 50 ppm or better.

FvM said:

In the latter case, both NCO outputs will slowly drift apart if they are not periodically synchronized. My favorite solution for similar situations is to synchronize either one PLL output or all PLL outputs of slave FPGAs with a master FPGA clock by using the dynamic phase shift feature of Altera PLLs. Frequency differences of several 100 ppm can be compensated this way, the typical crystal accuracy is 50 ppm or better.

Click to expand...

Along with what FvM has stated if the design does not allow for having a master clock source where you can use PLLs to phase align the clocks for the master and slave FPGAs, then you might be able to take a different approach that is used in video networking type systems, where a time sync is used to synchronize multiple counters across multiple boxes that are all running off different clock sources. in this case you would synchronize say the peak of the sine wave to this sync signal. Unfortunately you would also have to write your own NCO as Altera's implementation won't allow you to set a specific phase by writing the current starting value into the phase accumulation they use. But if you did write your own then you could continuously correct the phase of the two sinusoids at every sync. At most you would only be off by one NCO input clock.

Two fpga have different 50MHz clock source. The sync signal comes from an external cpu and it has 100ms period and 20ns pulse width but i can speed up the period.
So a slow drift could be happen.
I'd like to use ALTERA NCO where the input are:

MASTER CLK (50MHZ)
CLK ENABLE (25KHZ)
PHASE INCREMENT (output Frequency)
PHASE MODULATION
FREQUENCY MOD
RESET

Is it possible to correct dinamically the phase with sync signal or acting on clk enable is a better way?
I think that in my case i can't use the feature of altera PLL, but i'm not sure.

Let me know any new ideas...

Is it possible to correct dinamically the phase with sync signal or acting on clk enable is a better way?

Click to expand...

The sync signal has no correlation with the NCOs output sinusoid based on what you seem to be stating (comes from a uP), so no without access to the D register in the Altera NCO phase accumulator see the diagram below

You won't be able to adjust the phase of the NCO, The phase increment sets the increment value of the phase accumulator, it doesn't set the current phase of the output. I suppose you could slave one of the NCOs to the other and adjust the phase increment based on the error between the two sinusoids. You would have to make sure it has some filtering otherwise the phase of the sinusoid could wildly oscillate.

Altera's NCO doesn't appear to have any support for synchronizing multiple NCOs.

About the only way I can see this working is to send the current phase information from one of the NCOs (i.e. the master) and slave the other one to that phase using the enable to start/stop the sequence, but this would only work if the master NCO has a 50- MHz while the slave NCO is running at 50+ MHz (you can slow the slave down in this case when it starts to skew towards generating the output too early. The other direction can't be compensated for based on your current desire to use the Altera NCO, which isn't designed to synchronize with anything else (or at least looking over the User Guide doesn't make it obvious there is such a feature).

Hi,

Altera NCO has a phase input register and only clearing that register doesn't correct the phase of output signal.

Click to expand...

I'm not talking to clear any NCO register, I'm talking to clear the sine_generation_register.

NCO output frequency is much higher than the 70Hz.
Usually it goes into the sine generation unit. Here you have to do the syncing.

Klaus

KlausST, did you look at the block diagram of the Altera NCO I had in post #8?

The only way to align the two NCOs is to make both phase accumulators the same, but Altera's core does not allow that to be done. There isn't any way to also modify the waveform generation unit on-the-fly to shift the phase. At least both of these features are missing from my quick going over of the User Guide.

There isn't any way to also modify the waveform generation unit on-the-fly to shift the phase.

Click to expand...

The phase modulation input does exactly this. You can even disable the phase accumulator and supply your own phase, if you want to utilize primarily the optimized sine generation of the NCO core.

You effectively are attempting to estimate the initial phase offset, as well as the internal clock frequency offset. This can be done directly, or by using a PLL structure to successively alter the frequency.

For example, you can compute an estimate of clock rate by counting the number of cycles between markers. This gives you way to set the frequency modulation input. If you have direct access to the phase accumulator, you can determine a value to set for the phase modulation input in a very direct manner. Otherwise you can regenerate the value using the sine/cosine outputs, but this is much more difficult.

This will quickly sync the output to the pulses, causing a potentially large jump in phase. Normal frequency/phase updates should also be done when the phase accumulator is near +-90deg if you only have a sine wave output. This is because the derivative of the waveform is minimal at those times, so a small phase shift is even less noticeable.


A PLL structure allows you to do something similar by estimating the frequency and allowing the frequency to be slightly high/low in order to smoothly adjust the phase.