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[SOLVED] RE: PreCTS timing analysis encounter

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kenambo

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RE: PreCTS timing analysis encounter

Hi All,

I have input delays set as greater than the available clock periods. For example, in my constraint file Input delay for a pin is set as 25.5ns and I am using 8 ns period clock and the path has multicycle path of 3 periods.

So I m getting violation in preCTS stage as the delay is high compared to the clock period. Is there any way to ignore these violations or correct them?

Is this a valid constraint? If it is valid how to get preCTS analysis cleared?
if you guys need more details, let me know.

Thanks
 

Re: PreCTS timing analysis encounter

kenambo said:
Hi All,

I have input delays set as greater than the available clock periods. For example, in my constraint file Input delay for a pin is set as 25.5ns and I am using 8 ns period clock and the path has multicycle path of 3 periods.

So I m getting violation in preCTS stage as the delay is high compared to the clock period. Is there any way to ignore these violations or correct them?

Is this a valid constraint? If it is valid how to get preCTS analysis cleared?
if you guys need more details, let me know.

Thanks
Click to expand...

that doesn't sound right. first, why 25ns? who is generating these signals? another board?
there are many ways to ignore it, but I am not sure it makes sense for you to do so. the easiest way would be a false_path
 

Re: PreCTS timing analysis encounter

Input delay with 25,5 ns while the multicycle number is 3 ( x 8ns = 24 ns ).
Still obviously be a violation.

I am not sure what is the aim of 25,5. You need to check with logic design guys to be sure about this signal functions and waveform.
 

Re: PreCTS timing analysis encounter

Yes .

Maybe this constraint is because of CTS. Since I am checking with this constraint in PreCTS mode I m getting violations. Anyway, let me check with the design..
Thanks

- - - Updated - - -

It is the Input signal from outer environment. and Input delay is set as 25.5 ns... with respect to a virtual clock.
 

Re: PreCTS timing analysis encounter

So it looks like this has nothing to do with CTS, you would see the same violations before or after.

If the signal really has that behaviour, you have to design around it. Talk to the person that created the constraint about making it a false_path or a multicycle path that is > 25.5s.
 

Re: PreCTS timing analysis encounter

Yes , The signal has the constraint as above. But now multicycle path is changed to 4.

Thanks
 

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