library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity lcd is
port(clk : in std_logic;
RW: out std_logic;
RS: out std_logic;
E: out std_logic;
lcd_data: inout std_logic_vector(7 downto 0);
addr_sram : out std_logic_vector(19 downto 0);
data_sram : inout std_logic_vector(15 downto 0);
CE_N: out std_logic;
OE_N: out std_logic;
WE_N: out std_logic;
LB_N: out std_logic;
UB_N: out std_logic);
end lcd;
architecture beh of lcd is
signal lcd_enable: std_logic;
signal lcd_busy: std_logic;
signal busy: std_logic := '1';
signal a,b,c:integer := 0;
signal lcd_bus: std_logic_vector(9 downto 0);
signal data1: std_logic_vector(9 downto 0);
signal data2: std_logic_vector(9 downto 0);
signal addr1: std_logic_vector(19 downto 0):=x"00000";
signal r_reg: unsigned(19 downto 0):=x"00000";
signal r_inc: unsigned(19 downto 0);
type state_type is (power_up,initialize,addr_increment,b0,b2,b3,b4,b1,delay,ready,send);
signal state : state_type;
begin
WE_N<='1';
OE_N<='0';
CE_N<='0';
UB_N<='0';
LB_N<='0';
process(clk)
variable char: integer range 0 to 6 := 1;
variable clk_count: integer := 0;
begin
if(clk' event and clk='1') then
case state is
when power_up=>
clk_count := 0;
RS<= '0';
RW<= '0';
lcd_data<= "00110000";
state<=initialize;
when initialize=>
clk_count := clk_count+1;
if(clk_count <(2000)) then
lcd_data <= "00111100";
E<='1';
E<='0';
lcd_data <= "00001100";
E<='1';
E<='0';
lcd_data <= "00000001";
E<='1';
state <= initialize;
elsif(clk_count < (100000)) then
lcd_data <= "00000000";
E<='1';
E<='0';
lcd_data<="00001100";
E<='1';
E<='0';
lcd_data<="00000001";
E<='1';
state <= initialize;
elsif(clk_count<(100000)) then
lcd_data <= "00000000";
E<='0';
state<=initialize;
else
clk_count := 0;
state<=b0;
end if;
when b0=>
r_reg<= unsigned(addr1);
r_inc<=r_reg+1;
r_reg<=r_inc;
addr_sram<=std_logic_vector(r_reg);
data1(9 downto 8)<="10";
data2(9 downto 8)<="10";
data1(7 downto 0)<=data_sram(7 downto 0);
data2(7 downto 0)<=data_sram(15 downto 8);
b<=b+1;
state<=b2;
when b2=>
if(b<3) then
b<=b+1;
state<=b0;
else
b<=0;
state<=b1;
c<=c+1;
end if;
when b3=>
lcd_enable<='1';
lcd_bus(9 downto 8)<="00";
lcd_bus(7 downto 0)<="11000000";
c<=c+1;
state<=ready;
when b4=>
RS<='0';
RW<='0';
clk_count := clk_count+1;
if(clk_count<(2000)) then
lcd_data <= "00000001";
E<='1';
state<=b4;
elsif(clk_count<(100000)) then
lcd_data<="00000000";
E<='0';
state<=b4;
else
clk_count := 0;
c<=0;
r_reg<=unsigned(addr1);
r_inc<= r_reg+1;
r_reg<= r_inc;
addr_sram<=std_logic_vector(r_reg);
state<=b0;
end if;
when b1=>
lcd_enable<='1';
if(char<4) then
char := char+1;
end if;
case char is
when 2=>
lcd_bus<=data1;
state<=ready;
when 3=>
lcd_bus<=data2;
char := 1;
state<=ready;
when others=> lcd_enable<='0';
state<=addr_increment;
end case;
----------- wait for the enable signal
when ready=>
if(lcd_enable='1') then
busy<='1';
RS<=lcd_bus(9);
RW<=lcd_bus(8);
lcd_data<=lcd_bus(7 downto 0);
clk_count := 0;
state<=send;
else
busy<='0';
RS<='0';
RW<='0';
lcd_data<="00000000";
clk_count := 0;
state<=ready;
end if;
when send=>
busy<='1';
if(clk_count<(600)) then
busy<='1';
if(clk_count<(50)) then
E<='0';
elsif(clk_count<(200)) then
E<='1';
elsif(clk_count<(500)) then
E<='0';
end if;
clk_count := clk_count+1;
state<=send;
else
clk_count := 0;
state<=delay;
end if;
when delay=>
if(a<20000000) then
a<=a+1;
state<=delay;
else
a<=0;
state<=addr_increment;
end if;
when addr_increment=>
if(char=1 and c=8) then
state<=b3;
elsif(char=1 and c=17) then
state<=b4;
c<=0;
elsif(char=1) then
state<=b0;
else
state<=b1;
end if;
end case;
end if;
end process;
end beh;
r_reg<=unsigned(addr1);
r_inc<= r_reg+1;
r_reg<= r_inc;BTW where is this code that somehow manages to read in a text file and initializes a RAM?
